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    Semiconductor mismatch reduction
    1.
    发明授权
    Semiconductor mismatch reduction 有权
    半导体失配减少

    公开(公告)号：US09287252B2

    公开(公告)日：2016-03-15

    申请号：US13048411

    申请日：2011-03-15

    Applicant: Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    Inventor： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    IPC: H01L29/12 ,  H01L27/02

    CPC classification number: H01L27/0207

    Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

    Abstract translation: 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

    Methods for eliminating phase distortion in signals
    2.
    发明申请
    Methods for eliminating phase distortion in signals 有权
    消除信号相位失真的方法

    公开(公告)号：US20080297200A1

    公开(公告)日：2008-12-04

    申请号：US11807521

    申请日：2007-05-29

    Applicant: Ruey-Bin Sheen

    Inventor： Ruey-Bin Sheen

    IPC: G01R25/00

    CPC classification number: H03K5/1534 ,  H03K5/26

    Abstract: A circuit for reducing phase distortion of a first signal and a second signal is provided, wherein the first and the second signals are complementary. The circuit includes a detecting circuit for detecting a first edge of the first signal and a second edge of the second signal, wherein the second edge immediately follows the first edge and is in a same direction as the first edge; an output node; and a signal regenerator connected to the detecting circuit and the output node. The signal regenerator is configured to generate an output signal having an additional first edge and an additional second edge. The additional first edge and the additional second edge are opposite edges substantially aligned to the first edge and the second edge, respectively. The additional first edge and the additional second edge are immediate neighboring edges.

    Abstract translation: 提供了用于减少第一信号和第二信号的相位失真的电路，其中第一和第二信号是互补的。 该电路包括用于检测第一信号的第一边缘和第二信号的第二边缘的检测电路，其中第二边缘紧接着第一边缘并且处于与第一边缘相同的方向; 输出节点; 以及连接到检测电路和输出节点的信号再生器。 信号再生器被配置为产生具有附加的第一边缘和附加的第二边缘的输出信号。 附加的第一边缘和附加的第二边缘分别相对于第一边缘和第二边缘大致对准的相对边缘。 附加的第一边缘和附加的第二边缘是紧邻的边缘。

    System and method for calibrating on-die components
    3.
    发明授权
    System and method for calibrating on-die components 有权
    用于校准模内部件的系统和方法

    公开(公告)号：US07268712B1

    公开(公告)日：2007-09-11

    申请号：US11406947

    申请日：2006-04-18

    Applicant: Ruey-Bin Sheen

    Inventor： Ruey-Bin Sheen

    IPC: H03M1/10

    CPC classification number: H04L25/0278

    Abstract: An on-die calibration system includes an external reference component, a first and a second on-die adjustable components, and a calibration module coupled to the reference component, the first and second components, wherein the calibration module calibrates the first component according to the reference component and calibrates the second component according to the calibrated first component.

    Abstract translation: 片上校准系统包括外部参考部件，第一和第二管芯上可调节部件以及耦合到参考部件第一和第二部件的校准模块，其中校准模块根据第一和第二部件校准第一部件 参考组件，并根据校准的第一组件校准第二组件。

    Built-in self-test circuit for liquid crystal display source driver
    4.
    发明授权
    Built-in self-test circuit for liquid crystal display source driver 有权
    内置自检电路，用于液晶显示源驱动

    公开(公告)号：US08810268B2

    公开(公告)日：2014-08-19

    申请号：US12764346

    申请日：2010-04-21

    Applicant: Jui-Cheng Huang ,  Yung-Chow Peng ,  Ruey-Bin Sheen

    Inventor： Jui-Cheng Huang ,  Yung-Chow Peng ,  Ruey-Bin Sheen

    IPC: G01R31/3187

    CPC classification number: G09G3/3685 ,  G09G3/006 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/12

    Abstract: A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.

    Abstract translation: 用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置 作为比较。 第一输入信号和第二输入信号耦合到比较器。 第一输入信号是预定的参考电压电平。 第二输入信号是测试范围内的测试偏移电压。

    Semiconductor Mismatch Reduction
    5.
    发明申请
    Semiconductor Mismatch Reduction 有权
    半导体失配减少

    公开(公告)号：US20120235208A1

    公开(公告)日：2012-09-20

    申请号：US13048411

    申请日：2011-03-15

    Applicant: Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    Inventor： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

    IPC: H01L29/12 ,  H01L21/66

    CPC classification number: H01L27/0207

    Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

    Abstract translation: 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

    Clock and data recovery systems and methods
    9.
    发明申请
    Clock and data recovery systems and methods 审中-公开
    时钟和数据恢复系统和方法

    公开(公告)号：US20060039513A1

    公开(公告)日：2006-02-23

    申请号：US10919429

    申请日：2004-08-17

    Applicant: Ruey-Bin Sheen ,  Chih-Hsien Chang

    Inventor： Ruey-Bin Sheen ,  Chih-Hsien Chang

    IPC: H04L7/00

    CPC classification number: H04L7/0338

    Abstract: Methods of clock and data recovery (CDR) are provided. An exemplary method comprises extending the eye of the data stream by examining transitions of adjacent samples, detecting whether an island sample exists in each symbol according to the separation of the transitions, and altering the value of the neighboring samples near the island sample to be equal to the island sample.

    Abstract translation: 提供了时钟和数据恢复（CDR）的方法。 一种示例性方法包括通过检查相邻样本的转变来扩展数据流的眼睛，根据转换的间隔检测每个符号中是否存在岛样本，以及将岛样本附近的相邻样本的值改变为相等 到岛样品。

    Optimized layout cell
    10.
    发明授权
    Optimized layout cell 有权

    公开(公告)号：US12153869B2

    公开(公告)日：2024-11-26

    申请号：US18313844

    申请日：2023-05-08

    Applicant: Ruey-Bin Sheen ,  Tien-Chien Huang ,  Chuan-Yao Tan

    Inventor： Ruey-Bin Sheen ,  Tien-Chien Huang ,  Chuan-Yao Tan

    IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398

    Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

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