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公开(公告)号：US06631165B1
公开(公告)日：2003-10-07
申请号：US09388175
申请日：1999-09-01
申请人： Russell H. Lambert , Peter J. Hadinger , Denes L. Zsolnay , Bruce W. Evans , Shi-Ping Hsu , Gerard Roccanova
发明人： Russell H. Lambert , Peter J. Hadinger , Denes L. Zsolnay , Bruce W. Evans , Shi-Ping Hsu , Gerard Roccanova
IPC分类号： H04L2700
摘要： A method (100) and apparatus (400) for encoding and decoding data in a signal using notch depth modulation. The method (100) of data to be encoded in the signal. The method then notch filters (125) the signal according to the frequency notch representation of the data. The apparatus (400) for encoding data comprises an digitizer (405) to digitize the signal. A code former (420) provides the data to be encoded in the signal. A notch filter (430) notch filters the signal according to the data. Decoding the data converts the signal into a frequency domain representation (520) and determines the notch spectral content (525) of the signal at selected notch frequencies. The method (500) establishes notch thresholds (534) at each of the selected notch frequencies, then decodes the data (540) from the signal by comparing the notch spectral content to the notch thresholds.
摘要翻译： 一种用于使用陷波深度调制对信号中的数据进行编码和解码的方法（100）和装置（400）。 在信号中要编码的数据的方法（100）。 该方法然后根据数据的频率陷波表示来陷波滤波器（125）信号。 用于编码数据的装置（400）包括用于数字化信号的数字化仪（405）。 代码表（420）提供要在信号中编码的数据。 陷波滤波器（430）根据数据对信号进行陷波滤波。 对数据进行解码将信号转换为频域表示（520），并确定所选陷波频率处的信号的陷波频谱含量（525）。 方法（500）在每个选择的陷波频率处建立陷波阈值（534），然后通过将陷波频谱内容与陷波阈值进行比较来解码来自信号的数据（540）。
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公开(公告)号：US08000482B2
公开(公告)日：2011-08-16
申请号：US11197817
申请日：2005-08-05
IPC分类号： H04B15/00
CPC分类号： H04R3/005 , H04R2201/403
摘要： Apparatus and a corresponding method for processing speech signals in a noisy reverberant environment, such as an automobile. An array of microphones (10) receives speech signals from a relatively fixed source (12) and noise signals from multiple sources (32) reverberated over multiple paths. One of the microphones is designated a reference microphone and the processing system includes adaptive frequency impulse response (FIR) filters (24) enabled by speech detection circuitry (21) and coupled to the other microphones to align their output signals with the reference microphone output signal. The filtered signals are then combined in a summation circuit (18). Signal components derived from the speech signal combine coherently in the summation circuit, while noise signal components combine incoherently, resulting in composite output signal with an improved signal-to-noise ratio. The composite output signal is further processed in a speech conditioning circuit (20) to reduce the effects of reverberation.
摘要翻译： 用于在噪声混响环境（例如汽车）中处理语音信号的装置和相应方法。 麦克风阵列（10）从相对固定的源（12）接收语音信号，并且从多个源（32）的多个路径上混响的噪声信号。 麦克风中的一个被指定为参考麦克风，并且处理系统包括由语音检测电路（21）启用的自适应频率脉冲响应（FIR）滤波器（24），并且耦合到另一麦克风以将其输出信号与参考麦克风输出信号 。 滤波的信号然后在求和电路（18）中组合。 来自语音信号的信号分量在求和电路中相干地组合，而噪声信号分量非均匀地组合，导致具有改善的信噪比的复合输出信号。 复合输出信号在语音调理电路（20）中被进一步处理，以减少混响的影响。
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公开(公告)号：US06917318B2
公开(公告)日：2005-07-12
申请号：US10731667
申请日：2003-12-09
申请人： Russell H. Lambert
发明人： Russell H. Lambert
CPC分类号： H04W88/06 , H03M3/332 , H03M3/334 , H03M3/336 , H03M3/43 , H03M3/456 , H03M3/50 , H03M7/3008 , H03M7/3028 , H03M7/304 , H04W84/12
摘要： An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock reduction circuit. The modulator receives the analog signal and a feedback signal and, based there upon, produces a modulated signal at a modulator clock rate. The decimation filter couples to the modulator, receives the modulated signal, and decimates and filters the modulated signal to produce the digital data. The time dither clock reduction circuit receives the modulated signal and provides the feedback signal to the modulator. The time dither clock reduction circuit applies both clock reduction and time dithering to the modulated signal to produce the feedback signal. At each modulator clock cycle, the time dithering clock reduction circuit considers modulated signals for a dithering factor, N, previous modulator clock cycles and a modulated signal for a current modulator clock cycle. If at least one constraint is satisfied for the N previous modulator clock cycles, the time dithering clock reduction circuit is allowed to transition the feedback signal with the modulated signal. If not, the time dithering clock reduction circuit holds the prior value of the feedback signal. After a transition, a new dithering factor may be determined. The ADC may be contained in a wireless local area network (WLAN) transceiving integrated circuit that services voice communications in a WLAN with at least one other WLAN device.
摘要翻译： 模数转换器（ADC）将模拟信号转换为数字数据。 ADC包括调制器，抽取滤波器和时间抖动时钟降低电路。 调制器接收模拟信号和反馈信号，并且基于此，以调制器时钟速率产生调制信号。 抽取滤波器耦合到调制器，接收调制信号，并抽取和滤波调制信号以产生数字数据。 时间抖动时钟降低电路接收调制信号并向调制器提供反馈信号。 时间抖动时钟降低电路将时钟减少和时间抖动应用于调制信号以产生反馈信号。 在每个调制器时钟周期，时间抖动时钟降低电路考虑用于抖动因子N的调制信号，先前的调制器时钟周期和用于当前调制器时钟周期的调制信号。 如果对于N个先前的调制器时钟周期满足至少一个约束，则允许时间抖动时钟降低电路用调制信号转换反馈信号。 如果不是，则时间抖动时钟降低电路保持反馈信号的先前值。 转换后，可以确定新的抖动因子。 ADC可以包含在用至少一个其它WLAN设备来服务WLAN中的语音通信的无线局域网（WLAN）收发集成电路中。
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公开(公告)号：US06661360B2
公开(公告)日：2003-12-09
申请号：US10230692
申请日：2002-08-29
申请人： Russell H. Lambert
发明人： Russell H. Lambert
IPC分类号： H03M120
CPC分类号： H04W88/06 , H03M3/332 , H03M3/334 , H03M3/336 , H03M3/43 , H03M3/456 , H03M3/50 , H03M7/3008 , H03M7/3028 , H03M7/304 , H04W84/12
摘要： An Analog-to-Digital-Converter (ADC) converts an analog signal to digital data. The ADC includes a modulator, a decimation filter, and a time dither clock reduction circuit. The modulator receives the analog signal and a feedback signal and, based there upon, produces a modulated signal at a modulator clock rate. The decimation filter couples to the modulator, receives the modulated signal, and decimates and filters the modulated signal to produce the digital data. The time dither clock reduction circuit receives the modulated signal and provides the feedback signal to the modulator. The time dither clock reduction circuit applies both clock reduction and time dithering to the modulated signal to produce the feedback signal. At each modulator clock cycle, the time dithering clock reduction circuit considers modulated signals for a dithering factor, N, previous modulator clock cycles and a modulated signal for a current modulator clock cycle. If at least one constraint is satisfied for the N previous modulator clock cycles, the time dithering clock reduction circuit is allowed to transition the feedback signal with the modulated signal. If not, the time dithering clock reduction circuit holds the prior value of the feedback signal. After a transition, a new dithering factor may be determined. The ADC may be contained in a wireless local area network (WLAN) transceiving integrated circuit that services voice communications in a WLAN with at least one other WLAN device.
摘要翻译： 模数转换器（ADC）将模拟信号转换为数字数据。 ADC包括调制器，抽取滤波器和时间抖动时钟降低电路。 调制器接收模拟信号和反馈信号，并且基于此，以调制器时钟速率产生调制信号。 抽取滤波器耦合到调制器，接收调制信号，并抽取和滤波调制信号以产生数字数据。 时间抖动时钟降低电路接收调制信号并向调制器提供反馈信号。 时间抖动时钟降低电路将时钟减少和时间抖动应用于调制信号以产生反馈信号。 在每个调制器时钟周期，时间抖动时钟降低电路考虑用于抖动因子N的调制信号，先前的调制器时钟周期和用于当前调制器时钟周期的调制信号。 如果对于N个先前的调制器时钟周期满足至少一个约束，则允许时间抖动时钟降低电路用调制信号转换反馈信号。 如果不是，则时间抖动时钟降低电路保持反馈信号的先前值。 转换后，可以确定新的抖动因子。 ADC可以包含在用至少一个其它WLAN设备来服务WLAN中的语音通信的无线局域网（WLAN）收发集成电路中。
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公开(公告)号：US07031401B2
公开(公告)日：2006-04-18
申请号：US10230738
申请日：2002-08-29
申请人： Russell H. Lambert
发明人： Russell H. Lambert
CPC分类号： H04W88/06 , H03M3/332 , H03M3/334 , H03M3/336 , H03M3/43 , H03M3/456 , H03M3/50 , H03M7/3008 , H03M7/3028 , H03M7/304 , H04W84/12
摘要： A Digital-to-Analog-Converter (DAC) includes an interpolation filter, a modulator, and a time dither clock reduction circuit. The interpolation filter receives the digital data and interpolates and filters the digital data to produce an interpolated and filtered digital signal. The modulator receives the interpolated and filtered digital signal and a feedback signal. The modulator modulates the interpolated and filtered digital signal based upon the feedback signal to produce a modulated signal at a modulator clock rate. The time dither clock reduction circuit receives the modulated signal and applies both clock reduction and time dithering to the modulated signal to produce a time dithered/clock reduced modulated signal. The time dithered/clock reduced modulated signal serves as the analog signal and also serves as the feedback signal. The DAC may be contained in a wireless local area network (WLAN) transceiving integrated circuit that services voice communications in a WLAN with at least one other WLAN device.
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