公开(公告)号：US20140312383A1

公开(公告)日：2014-10-23

申请号：US14322346

申请日：2014-07-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk SONG ,  Jae Hoon Park ,  Dong Soo Seo ,  Chang Su Jang

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L21/265 ,  H01L21/26513 ,  H01L29/36 ,  H01L29/66348

Abstract: A power semiconductor device may include: abase substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Abstract translation: 功率半导体器件可以包括：包括第一导电型漂移层的基板; 设置在所述基底基板的另一个表面上的第二导电型半导体基板; 第一导电型扩散层，设置在所述基底衬底中，其杂质浓度高于所述漂移层的杂质浓度; 设置在所述基底基板的一个表面内的第二导电型阱层; 从包括所述阱层的所述基底基板的一个表面形成的沟槽，以在深度方向上穿过所述扩散层; 设置在所述基底基板的表面上的第一绝缘膜; 以及设置在沟槽中的第一电极。 扩散层在横向上的杂质掺杂浓度的峰值点可以位于与沟槽的侧表面接触的区域中。

公开(公告)号：US20140159104A1

公开(公告)日：2014-06-12

申请号：US13829896

申请日：2013-03-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon PARK ,  In Hyuk SONG ,  Kee Ju UM ,  Dong Soo SEO

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: There is provided a semiconductor device including: a first semiconductor region having a first conductivity; a second semiconductor region having a second conductivity and formed on a surface of the first semiconductor region; a third semiconductor region having the first conductivity and formed on a surface of the second semiconductor region; a gate electrode disposed in a trench that passes through the third semiconductor region in a depth direction and extends to an inside of the second semiconductor region; a first insulation layer formed between the gate electrode and the third semiconductor region; a second insulation layer formed between the gate electrode and the second semiconductor region; and a fourth semiconductor region having the second conductivity and formed in a portion of a surface of the third semiconductor region, wherein a thickness of a portion of the second insulation layer is greater than that of the first insulation layer.

Abstract translation: 提供了一种半导体器件，包括：具有第一导电性的第一半导体区域; 具有第二导电性并形成在第一半导体区域的表面上的第二半导体区域; 具有第一导电性并形成在第二半导体区域的表面上的第三半导体区域; 设置在沟槽中的栅电极，所述沟槽在深度方向上穿过所述第三半导体区域并延伸到所述第二半导体区域的内部; 形成在所述栅极电极和所述第三半导体区域之间的第一绝缘层; 形成在栅电极和第二半导体区之间的第二绝缘层; 以及具有第二导电性并形成在第三半导体区域的表面的一部分中的第四半导体区域，其中第二绝缘层的一部分的厚度大于第一绝缘层的厚度。

公开(公告)号：US20160005842A1

公开(公告)日：2016-01-07

申请号：US14495887

申请日：2014-09-25

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  Chang Su JANG ,  Kyu Hyun MO ,  In Hyuk SONG

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/66348 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/7621 ,  H01L29/0649 ,  H01L29/7397

Abstract: A power semiconductor device may include a drift region including a base layer and a surface semiconductor layer disposed on the base layer and having a first conductivity type; a field insulating layer disposed on the base layer, embedded in the surface semiconductor layer, and including an opening portion; and a collector region disposed below the base layer and having a second conductivity type. The field insulating layer is formed in the drift region to limit movement of holes, whereby conduction loss of the power semiconductor device may be significantly decreased.

Abstract translation: 功率半导体器件可以包括漂移区，包括基底层和设置在基底层上并具有第一导电类型的表面半导体层; 设置在所述基底层上的场绝缘层，嵌入在所述表面半导体层中，并且包括开口部; 以及设置在所述基底层下方并具有第二导电类型的集电极区域。 在漂移区域中形成场绝缘层以限制空穴的移动，从而可以显着降低功率半导体器件的导通损耗。

公开(公告)号：US20150364585A1

公开(公告)日：2015-12-17

申请号：US14470355

申请日：2014-08-27

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： In Hyuk SONG ,  Dong Soo SEO ,  Ji Hye KIM ,  Chang Su JANG ,  Jae Hoon PARK

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7397

Abstract: A power semiconductor device may include: an n-drift part; a gate disposed in an upper portion of the n-drift part; an active part disposed to be in contact with the gate; an emitter part disposed in the active part and disposed to be in contact with the gate; an inactive part disposed to be spaced apart from the active part; a floating part disposed in the inactive part; and a dummy gate disposed to surround the inactive part in order to prevent a hole pass between the active part and the inactive part.

Abstract translation: 功率半导体器件可以包括：n漂移部分; 设置在所述n漂移部的上部的栅极; 设置成与门接触的有源部分; 发射极部，设置在所述有源部中并被设置成与所述栅极接触; 设置成与所述有源部分间隔开的非活性部分; 设置在非活动部分中的浮动部分; 以及设置成围绕不活动部分的虚拟门，以便防止活动部分和非活动部分之间的穿孔。

公开(公告)号：US20150187921A1

公开(公告)日：2015-07-02

申请号：US14273159

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  In Hyuk SONG ,  Dong Soo SEO ,  Ji Yeon OH ,  Kee Ju UM

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1025 ,  H01L29/1095 ,  H01L29/267 ,  H01L29/7802 ,  H01L29/7813

Abstract: A power semiconductor device may include a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed in an upper portion of the first semiconductor region; a third semiconductor region having a first conductivity type and formed in an upper portion of the second semiconductor region; and a trench gate formed by penetrating from the third semiconductor region to the first semiconductor region. A portion of at least one of the first semiconductor region, the second semiconductor region, and the third semiconductor region may include a device protection material of which a conduction band has a main state and a satellite state in an E-k diagram, and a curvature of the device protection material in the satellite state may be lower than a curvature thereof in the main state in the E-k diagram.

Abstract translation: 功率半导体器件可以包括具有第一导电类型的第一半导体区域; 具有第二导电类型并形成在第一半导体区域的上部的第二半导体区域; 具有第一导电类型并形成在第二半导体区域的上部的第三半导体区域; 以及通过从第三半导体区域穿透到第一半导体区域而形成的沟槽栅极。 第一半导体区域，第二半导体区域和第三半导体区域中的至少一个的一部分可以包括在Ek图中导带具有主状态和卫星状态的器件保护材料，以及曲率 处于卫星状态的器件保护材料可能低于Ek图中主状态下的曲率。

公开(公告)号：US20150187919A1

公开(公告)日：2015-07-02

申请号：US14221972

申请日：2014-03-21

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk SONG ,  Dong Soo SEO ,  Kyu Hyun MO ,  Chang Su JANG ,  Jae Hoon PARK

IPC: H01L29/739 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/74 ,  H01L29/7813

Abstract: A provided a power semiconductor device may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed on the first semiconductor region; a plurality of trench gates formed to penetrate through the second semiconductor region and lengthily formed in one direction; and a third semiconductor region of the first conductive type formed on the second semiconductor region, formed at least partially in a length direction between the plurality of trench gates, and formed to contact one side of an adjacent trench gate in a width direction.

Abstract translation: 提供功率半导体器件的A可以包括：第一导电类型的第一半导体区域; 形成在第一半导体区域上的第二导电类型的第二半导体区域; 多个沟槽栅极，形成为穿过所述第二半导体区域并且沿一个方向长时间地形成; 以及第一导电类型的第三半导体区域，形成在所述第二半导体区域上，至少部分地在所述多个沟槽栅极之间的长度方向上形成，并且形成为在宽度方向上接触相邻沟槽栅极的一侧。

公开(公告)号：US20150187868A1

公开(公告)日：2015-07-02

申请号：US14243873

申请日：2014-04-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  Ji Hye KIM ,  Kyu Hyun MO ,  Dong Soo SEO ,  In Hyuk SONG

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/063 ,  H01L29/1095 ,  H01L29/7397

Abstract: A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.

Abstract translation: 功率半导体器件可以包括：有源区域，其中电流流过当器件导通时形成的沟道; 设置在所述有源区域周围的端接区域; 第一导电类型的第一半导体区域，设置在从有源区域到端接区域的方向上的端接区域中; 以及第二导电类型的第二半导体区域，其设置在从所述有源区域到所述端接区域的方向上的所述端接区域中，所述第一半导体区域和所述第二半导体区域交替布置。

公开(公告)号：US20150144994A1

公开(公告)日：2015-05-28

申请号：US14329378

申请日：2014-07-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Kyu SUNG ,  Dong Soo SEO ,  Chang Su Jang ,  Jae Hoon PARK ,  In Hyuk SONG

IPC: H01L29/739 ,  H01L29/417

CPC classification number: H01L29/7397 ,  H01L29/4232

Abstract: A power semiconductor device may include: a first semiconductor layer having a first conductivity type; a second semiconductor layer formed on the first semiconductor layer, having a concentration of impurities higher than that of the first semiconductor layer, and having the first conductivity type; a third semiconductor layer formed on the second semiconductor layer and having a second conductivity type; a fourth semiconductor layer formed in an upper surface of the third semiconductor layer and having the first conductivity type; and trench gates penetrating from the fourth semiconductor layer into a portion of the first semiconductor layer and having gate insulating layers formed on surfaces thereof. The trench gates have a first gate, a second gate, and a third gate are sequentially disposed from a lower portion thereof, and the first gate, the second gate, and the third gate are insulated from each other by gate insulating films.

Abstract translation: 功率半导体器件可以包括：具有第一导电类型的第一半导体层; 形成在第一半导体层上的第二半导体层，其杂质浓度高于第一半导体层，其具有第一导电类型; 形成在第二半导体层上并具有第二导电类型的第三半导体层; 形成在第三半导体层的上表面并具有第一导电类型的第四半导体层; 以及从第四半导体层穿入第一半导体层的一部分并且在其表面上形成有栅极绝缘层的沟槽栅极。 沟槽栅极具有第一栅极，第二栅极和第三栅极，从其下部依次配置，并且第一栅极，第二栅极和第三栅极通过栅极绝缘膜彼此绝缘。

公开(公告)号：US20150123164A1

公开(公告)日：2015-05-07

申请号：US14273341

申请日：2014-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon PARK ,  Jae Kyu SUNG ,  In Hyuk SONG ,  Ji Yeon OH ,  Dong Soo SEO

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/74 ,  H01L29/7813 ,  H01L29/7827

Abstract: A power semiconductor device may include a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper portion of the first semiconductor region; a first conductivity type third semiconductor region formed in an upper inner side of the second semiconductor region; a trench gate formed to penetrate through a portion of the first semiconductor region from the third semiconductor region; and a first conductivity type fourth semiconductor region formed below the second semiconductor region while being spaced apart from the trench gate.

Abstract translation: 功率半导体器件可以包括第一导电类型的第一半导体区域; 形成在所述第一半导体区域的上部的第二导电类型的第二半导体区域; 形成在第二半导体区域的上内侧的第一导电型第三半导体区域; 形成为从第三半导体区域穿过第一半导体区域的一部分的沟槽栅极; 以及在与所述沟槽栅极间隔开的状态下，形成在所述第二半导体区域的下方的第一导电型第四半导体区域

公开(公告)号：US20150087117A1

公开(公告)日：2015-03-26

申请号：US14559384

申请日：2014-12-03

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk SONG ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/265 ,  H01L29/10 ,  H01L21/324

CPC classification number: H01L29/6634 ,  H01L21/046 ,  H01L21/22 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66674 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/7825

Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract translation: 本发明公开了一种功率半导体器件，包括：具有一个表面和另一个表面并由第一导电型漂移层形成的基底基板; 形成在所述基底基板的一个表面上并且具有比所述第一导电型漂移层的浓度高的浓度的第一导电型扩散层; 以及形成为从厚度方向包括第二导电类型阱层的基底基板的一个表面穿过第二导电类型阱层和第一导电型扩散层的沟槽。