公开(公告)号：US20140291722A1

公开(公告)日：2014-10-02

申请号：US13937589

申请日：2013-07-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Dong Soo SEO ,  Jaehoon PARK ,  Kee Ju UM ,  Chang Su JANG ,  In Hyuk SONG

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/7395 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/7397

Abstract: There is provided a power semiconductor device, including a plurality of trench gates formed to be spaced apart from each other by a predetermined distance, a current increasing part formed between the trench gates and including a first conductivity-type emitter layer and a gate oxide formed on a surface of the trench gate, and an immunity improving part formed between the trench gates and including a second conductivity-type body layer, a preventing film formed on the surface of the trench gate, and a gate oxide having a thickness less than that the gate oxide of the current increasing part.

Abstract translation: 提供了一种功率半导体器件，包括形成为彼此间隔开预定距离的多个沟槽栅极，形成在沟槽栅极之间并包括第一导电型发射极层和形成的栅极氧化物的电流增加部分 在所述沟槽栅极的表面上形成的抗扰度改善部以及形成在所述沟槽栅极之间并且包括第二导电型体层的抗扰度改善部，以及形成在所述沟槽栅极的表面上的防止膜和厚度小于所述沟槽栅极的厚度的栅极氧化物。 电流增加部分的栅极氧化物。

公开(公告)号：US20140167123A1

公开(公告)日：2014-06-19

申请号：US14100949

申请日：2013-12-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Soo KIM ,  Bum Seok SUH ,  In Wha JEONG ,  Ji Hyun PARK ,  Jaehoon PARK

IPC: H01L29/417 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L29/0653 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66568 ,  H01L29/7827

Abstract: There is provided a power semiconductor device including: a body region having a first conductivity; a well formed in an upper portion of the body region and having a second conductivity; and a conductive via formed in the body region while traversing the well.

Abstract translation: 提供了一种功率半导体器件，包括：具有第一导电性的主体区域; 在所述身体区域的上部中良好地形成并且具有第二导电性; 以及在穿过井时在体区中形成的导电通孔。

公开(公告)号：US20140159104A1

公开(公告)日：2014-06-12

申请号：US13829896

申请日：2013-03-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon PARK ,  In Hyuk SONG ,  Kee Ju UM ,  Dong Soo SEO

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: There is provided a semiconductor device including: a first semiconductor region having a first conductivity; a second semiconductor region having a second conductivity and formed on a surface of the first semiconductor region; a third semiconductor region having the first conductivity and formed on a surface of the second semiconductor region; a gate electrode disposed in a trench that passes through the third semiconductor region in a depth direction and extends to an inside of the second semiconductor region; a first insulation layer formed between the gate electrode and the third semiconductor region; a second insulation layer formed between the gate electrode and the second semiconductor region; and a fourth semiconductor region having the second conductivity and formed in a portion of a surface of the third semiconductor region, wherein a thickness of a portion of the second insulation layer is greater than that of the first insulation layer.

Abstract translation: 提供了一种半导体器件，包括：具有第一导电性的第一半导体区域; 具有第二导电性并形成在第一半导体区域的表面上的第二半导体区域; 具有第一导电性并形成在第二半导体区域的表面上的第三半导体区域; 设置在沟槽中的栅电极，所述沟槽在深度方向上穿过所述第三半导体区域并延伸到所述第二半导体区域的内部; 形成在所述栅极电极和所述第三半导体区域之间的第一绝缘层; 形成在栅电极和第二半导体区之间的第二绝缘层; 以及具有第二导电性并形成在第三半导体区域的表面的一部分中的第四半导体区域，其中第二绝缘层的一部分的厚度大于第一绝缘层的厚度。

公开(公告)号：US20150076652A1

公开(公告)日：2015-03-19

申请号：US14101066

申请日：2013-12-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Chang Su JANG ,  Kee Ju UM ,  In Hyuk SONG ,  Jaehoon PARK ,  Dong Soo SEO

IPC: H01L29/06 ,  H01L29/861

CPC classification number: H01L29/861 ,  H01L29/0615

Abstract: There is provided a power semiconductor device, including: a first semiconductor layer of a first conductive type having a thickness of t1 so as to withstand a reverse voltage of 600V; and a second semiconductor layer of a second conductive type formed inside an upper portion of the first semiconductor layer and having a thickness of t2, wherein t1/t2 is 15 to 18.

Abstract translation: 提供了一种功率半导体器件，包括：具有厚度为t1的第一导电类型的第一半导体层，以承受600V的反向电压; 以及第二导电类型的第二半导体层，形成在所述第一半导体层的上部内并具有厚度t2，其中t1 / t2为15至18。

公开(公告)号：US20140239344A1

公开(公告)日：2014-08-28

申请号：US13890680

申请日：2013-05-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon PARK ,  In Hyuk SONG ,  Dong Soo SEO ,  Kwang Soo KIM ,  Kee Ju UM

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/66348 ,  H01L27/0817 ,  H01L27/088 ,  H01L27/0921 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/41733 ,  H01L29/4232 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66477 ,  H01L29/66484 ,  H01L29/66954 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/768 ,  H01L29/78 ,  H01L31/111 ,  H01L31/1113 ,  H01L51/0512

Abstract: There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer.

Abstract translation: 提供了一种功率半导体器件，包括第一导电型漂移层; 形成在漂移层上的第二导电型体层，形成在漂移层下面的第二导电型集电极层; 通过贯穿本体层和漂移层的一部分而形成的第一栅极，形成在主体层中并形成为与第一栅极间隔开的第一导电型发射极层，覆盖主体层的上部的第二栅极 和发射极层，并且在第一栅极上形成为平面型栅极，以及在第一和第二栅极的接触表面之间形成的偏析阻挡层，其具有主体层，发射极层和漂移层。

公开(公告)号：US20140138736A1

公开(公告)日：2014-05-22

申请号：US13751916

申请日：2013-01-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon PARK ,  Chang Su JANG ,  In Hyuk SONG ,  Kee Ju UM ,  Dong Soo SEO

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/1095

Abstract: There is provided an insulated gate bipolar transistor including: a first semiconductor area of a first conductivity type; a second semiconductor area of a second conductivity type formed on one surface of the first semiconductor area; third semiconductor areas of the first conductivity type continuously formed in a length direction on one surface of the second semiconductor area; a plurality of trenches formed between the third semiconductor areas, extending to an inside of the second semiconductor area, and being continuous in the length direction; a fourth semiconductor area of the second conductivity type formed on one surface of the third semiconductor areas, insulation layers formed inside the trenches; gate electrodes buried inside the insulation layers; and a barrier layer formed in at least one of locations corresponding to the third semiconductor areas inside the second semiconductor area.

Abstract translation: 提供了一种绝缘栅双极晶体管，包括：第一导电类型的第一半导体区域; 形成在第一半导体区域的一个表面上的第二导电类型的第二半导体区域; 在第二半导体区域的一个表面上沿长度方向连续形成的第一导电类型的第三半导体区域; 多个沟槽，形成在第三半导体区域之间，延伸到第二半导体区域的内部，并且在长度方向上是连续的; 形成在第三半导体区域的一个表面上的第二导电类型的第四半导体区域，形成在沟槽内的绝缘层; 掩埋在绝缘层内的栅电极; 以及形成在与所述第二半导体区域内的所述第三半导体区域对应的位置中的至少一个的阻挡层。

公开(公告)号：US20140117405A1

公开(公告)日：2014-05-01

申请号：US13746616

申请日：2013-01-22

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon PARK ,  Chang Su JANG ,  In Hyuk SONG ,  Kee Ju UM ,  Dong Soo SEO

IPC: H01L29/739

CPC classification number: H01L29/7397

Abstract: There is provided a semiconductor device including: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed on one surface of the first semiconductor region; a third semiconductor region having a first conductivity type and formed on one surface of the second semiconductor region; a gate electrode formed in a trench penetrating through the second semiconductor region and the third semiconductor region to reach an interior of the first semiconductor region; and a hole injection unit formed between the gate electrode and the first semiconductor region.

Abstract translation: 提供一种半导体器件，包括：具有第一导电类型的第一半导体区域; 具有第二导电类型并形成在第一半导体区域的一个表面上的第二半导体区域; 具有第一导电类型并形成在第二半导体区域的一个表面上的第三半导体区域; 形成在穿过所述第二半导体区域的沟槽和所述第三半导体区域中以到达所述第一半导体区域的内部的栅电极; 以及形成在所述栅极电极和所述第一半导体区域之间的空穴注入单元。