公开(公告)号：US20250140309A1

公开(公告)日：2025-05-01

申请号：US18653285

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongjin Yoo ,  Wangsoo KIM ,  Junsub Yoon

IPC: G11C11/4099 ,  G11C5/10 ,  G11C11/4093

Abstract: A memory device includes a reference voltage generator configured to generate a reference voltage, and a data input/output (I/O) buffer configured to receive a data signal having a first phase, generate a phase control signal having a second phase opposite to the first phase, and generate an output signal based on the data signal, the phase control signal, and the reference voltage.

公开(公告)号：US11888489B2

公开(公告)日：2024-01-30

申请号：US17888199

申请日：2022-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsub Yoon ,  Hun-Dae Choi

IPC: H03L7/081 ,  G11C7/22 ,  H03L7/083

CPC classification number: H03L7/0818 ,  G11C7/222 ,  G11C7/225 ,  H03L7/083 ,  H03L7/0814 ,  H03L7/0816

Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

公开(公告)号：US20240313750A1

公开(公告)日：2024-09-19

申请号：US18239450

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junsub Yoon ,  Jang-Woo Ryu

IPC: H03K5/08 ,  H03K5/131 ,  H03K5/133

CPC classification number: H03K5/088 ,  H03K5/131 ,  H03K5/133

Abstract: A clock signal synchronization circuit includes a delay line configured to delay an input clock signal in response to a delay control signal to output an output clock signal, a replica circuit configured to delay the output clock signal to output a feedback clock signal, a phase detector configured to compare the input clock signal and the feedback clock signal with each other to detect a phase difference, and a delay control circuit configured to generate the delay control signal based on the phase difference. The replica circuit may delay the output clock signal based on an operation mode of a memory device to output the feedback clock signal.

公开(公告)号：US11750181B2

公开(公告)日：2023-09-05

申请号：US17575020

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsub Yoon

IPC: G11C11/4093 ,  G11C11/4076 ,  H03K5/133 ,  H03K5/00

CPC classification number: H03K5/133 ,  G11C11/4076 ,  G11C11/4093 ,  H03K2005/00052

Abstract: Provided are a digital phase interpolator, a clock signal generator, and a volatile memory device including the clock signal generator. The clock signal generator includes an internal signal generator configured to generate a first internal signal and a second internal signal, which mutually have a phase difference, based on an external clock signal, a first phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a first control signal and generate a first interpolation signal, a second phase interpolator configured to interpolate the first internal signal with the second internal signal in response to a second control signal and generate a second interpolation signal, and a selector configured to select any one of the first interpolation signal and the second interpolation signal in response to a selection signal and output the selected interpolation signal as an internal clock signal.