公开(公告)号：US20240186282A1

公开(公告)日：2024-06-06

申请号：US18239454

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin Kim ,  Minwoo Rhee ,  Ilyoung Han ,  Sujie Kang ,  Juno Kim ,  Daeho Min ,  Kyeongbin Lim

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L2224/75252 ,  H01L2224/75735 ,  H01L2224/75745 ,  H01L2224/75804 ,  H01L2224/75841 ,  H01L2924/2064

Abstract: A die bonding apparatus comprising a stage configured to support a first die, a pickup head configured to pick up a second die, regions of magnetic materials arranged on the first die and the second die, an electromagnet arranged on a surface of the pickup head or the stage; and a controller configured to apply a current to the electromagnet to generate a magnetic field when the first die and the second die are disposed at a predetermined distance from each other in a vertical direction. As a result of the magnetic field generated by the electromagnet, the regions of magnetic material arranged on first die and the second die are aligned with one another in the vertical direction.

公开(公告)号：US20240170445A1

公开(公告)日：2024-05-23

申请号：US18379956

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juno Kim ,  Minwoo Rhee ,  Ilyoung Han ,  Juhyung Lee ,  Kyeongbin Lim

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L24/80 ,  H01L22/12 ,  H01L2224/80224 ,  H01L2224/8023 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908

Abstract: Provided is a method of manufacturing a semiconductor package, the method including: providing a first semiconductor die on a stage; bonding a second semiconductor die to the first semiconductor die to each other; applying heat to a surface of the second semiconductor die, which is opposite to a bonding interface of the first semiconductor die and the second semiconductor die; and measuring a temperature change on the surface of the second semiconductor die to which the heat is applied to inspect a state of the bonding interface.

公开(公告)号：US11837573B2

公开(公告)日：2023-12-05

申请号：US17166805

申请日：2021-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyung Kim ,  Joongha Lee ,  Sangha Park ,  Sunghyup Kim ,  Kyeongbin Lim

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L2224/75252 ,  H01L2224/75303 ,  H01L2224/75502 ,  H01L2924/3511

Abstract: A chip bonding apparatus includes: a bonding contact configured to apply a bonding force to a semiconductor chip disposed on a substrate, the bonding contact having a first surface configured to face the semiconductor chip and a second surface opposite the first surface, the bonding contact including a protruding portion on the first surface, the protruding portion configured to contact the semiconductor chip, the bonding contact including a cavity formed in a region vertically overlapping the protruding portion, a heater disposed to be in contact with the second surface of the bonding contact to cover the cavity, and configured to heat the bonding contact, a bonding head disposed above the heater and configured to transmit the bonding force, and a partition wall structure protruding from a bottom surface of the cavity to partition an inner space of the cavity.

公开(公告)号：US20210398935A1

公开(公告)日：2021-12-23

申请号：US17166805

申请日：2021-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyung Kim ,  Joongha Lee ,  Sangha Park ,  Sunghyup Kim ,  Kyeongbin Lim

IPC: H01L23/00

Abstract: A chip bonding apparatus includes: a bonding contact configured to apply a bonding force to a semiconductor chip disposed on a substrate, the bonding contact having a first surface configured to face the semiconductor chip and a second surface opposite the first surface, the bonding contact including a protruding portion on the first surface, the protruding portion configured to contact the semiconductor chip, the bonding contact including a cavity formed in a region vertically overlapping the protruding portion, a heater disposed to be in contact with the second surface of the bonding contact to cover the cavity, and configured to heat the bonding contact, a bonding head disposed above the heater and configured to transmit the bonding force, and a partition wall structure protruding from a bottom surface of the cavity to partition an inner space of the cavity.

公开(公告)号：US20250070079A1

公开(公告)日：2025-02-27

申请号：US18622040

申请日：2024-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： YongChul SHIN ,  Minwoo Rhee ,  Sujie Kang ,  Sun-woo Park ,  Nungpyo Hong ,  Kyeongbin Lim

IPC: H01L23/00 ,  B32B43/00 ,  H01L21/78

Abstract: A semiconductor package manufacturing method includes: bonding a carrier to a wafer; dicing the wafer together with the carrier which is bonded to the wafer into a plurality of die-carrier assemblies, each of the plurality of die-carrier assemblies including a die and a carrier piece bonded to the die; disposing the plurality of die-carrier assemblies on a target substrate; and separating the carrier pieces from the plurality of die-carrier assemblies by irradiating the plurality of die-carrier assemblies with light.

公开(公告)号：US20240145416A1

公开(公告)日：2024-05-02

申请号：US18384250

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyoung CHOI ,  Minwoo Rhee ,  Sungyoung Yoon ,  Jaehyun Phee ,  Bumki Moon ,  Kyeongbin Lim

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/03 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/03444 ,  H01L2224/05147 ,  H01L2224/05447 ,  H01L2224/08145

Abstract: A substrate bonding method includes: forming first plasma on a bonding surface of a first substrate at atmospheric pressure by using a mixed gas including an inert gas and water vapor, to thereby perform surface activation treatment on the bonding surface of the first substrate; forming second plasma on a bonding surface of a second substrate at atmospheric pressure by using the mixed gas, to thereby perform surface activation treatment on the bonding surface of the second substrate; bonding the bonding surface of the first substrate and the bonding surface of the second substrate to each other; and moving each of the first substrate and the second substrate at a constant speed in a region above a linear reactor in which the first plasma and the second plasma are formed.

公开(公告)号：US11581188B2

公开(公告)日：2023-02-14

申请号：US16842083

申请日：2020-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyung Kim ,  Kyeongbin Lim ,  Minsoo Han ,  Minwoo Rhee ,  Inbae Chang

IPC: H01L21/18 ,  B32B37/00 ,  B23K20/10 ,  H01L21/20 ,  H01L21/683 ,  H01L21/687 ,  H01L21/67 ,  H05K13/08 ,  B32B41/00 ,  B32B37/10 ,  B32B38/18

Abstract: A substrate bonding apparatus for bonding a first substrate to a second substrate includes a first bonding chuck supporting the first substrate, a second bonding chuck disposed above the first bonding chuck and supporting the second substrate, a resonant frequency detector detecting a resonant frequency of a bonded structure with the first substrate and the second substrate which are at least partially bonded to each other, and a controller controlling a distance between the first bonding chuck and the second bonding chuck according to the detected resonant frequency of the bonded structure.

公开(公告)号：US20240321805A1

公开(公告)日：2024-09-26

申请号：US18405791

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungho Hahn ,  Wooyoung Kim ,  Minwoo Rhee ,  Bumki Moon ,  Kyeongbin Lim

IPC: H01L23/00

CPC classification number: H01L24/27 ,  H01L2224/27614 ,  H01L2224/27616 ,  H01L2224/27848 ,  H01L2924/1434

Abstract: A method of manufacturing a semiconductor device includes preparing a first substrate and a second substrate respectively including a bonding layer having metal pads and a dielectric layer, performing a planarization process on a surface of the bonding layer of each of the first and second substrates, applying wet atomic layer etching to the surface of the bonding layer so that a surface of the metal pad is recessed to a target depth, and bonding the bonding layer of the first substrate to the bonding layer of the second substrate using an annealing process.

公开(公告)号：US11443965B2

公开(公告)日：2022-09-13

申请号：US16747783

申请日：2020-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeongbin Lim ,  Hyeonjun Yun ,  Gwanghee Jo ,  Jewon Lee ,  Minsoo Han ,  Junhyung Kim ,  Seungdae Seok

IPC: H01L21/67 ,  H01L21/683 ,  H01L23/00 ,  H01L21/20

Abstract: A wafer bonding apparatus includes lower and upper stages, lower and upper push rods, a position detection sensor, and processing circuitry. The stages may vacuum suction respective wafers on respective surfaces of the stages based on a vacuum pressure being supplied to respective suction holes in the respective surfaces from a vacuum pump. The push rods are movable through respective center holes in the stages to apply pressure to respective middle regions of the respective wafers. The position detection sensor may generate information indicating a bonding propagation position of the wafers based on detecting at least one wafer through a detection hole in at least one stage. The processing circuitry may process the information to detect the bonding propagation position and cause a change of at least one of a ratio of protruding lengths of the push rods, or a ratio of suction areas of the stages.

公开(公告)号：US20250054878A1

公开(公告)日：2025-02-13

申请号：US18632437

申请日：2024-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujie Kang ,  Minsoo Han ,  Minwoo Rhee ,  Kyoungwhan Oh ,  Kyeongbin Lim

IPC: H01L23/00 ,  H01L21/66

Abstract: A warpage control method includes measuring displacement in a vertical direction perpendicular to a front surface of a wafer and dividing the front surface of the wafer into a first stress region with a negative displacement value and a second stress region with a positive displacement value, to thereby derive a warpage model, defining a portion of a region, overlapping the first stress region, on the front surface of the wafer as a first compensation region based on the warpage model and defining a region, other than the first compensation region, on the front surface of the wafer as a second compensation region based on the warpage model, to thereby derive a stress compensation film pattern model, and forming a mask pattern in a region on a back surface of the wafer.