公开(公告)号：US20230207417A1

公开(公告)日：2023-06-29

申请号：US17952841

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSANG CHO ,  HEESEOK LEE ,  YUNHYEOK IM

IPC: H01L23/367 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/373 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L25/105 ,  H01L24/16 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/3736 ,  H01L23/13 ,  H01L23/315 ,  H01L23/3135 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1094 ,  H01L2225/1058 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L24/48 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2924/3511 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1811 ,  H01L2924/182

Abstract: A semiconductor package includes a first interconnection structure, a first semiconductor chip on the first interconnection structure, an encapsulant covering the first semiconductor chip, a second interconnection structure disposed on the first semiconductor chip and the encapsulant, including a plurality of interconnection layers, and having an opening having a step portion, exposing a portion of an upper surface of at least one of the plurality of interconnection layers, and a heat dissipation pattern disposed in the opening, passing through the encapsulant and in contact with at least a portion of an upper surface of the first semiconductor chip, and including a material having a thermal conductivity higher than thermal conductivity of silicon (Si). The heat dissipation pattern includes a lower portion having a first width, and an upper portion disposed on the lower portion and having a second width greater than the first width, and the upper portion of the heat dissipation pattern is in contact with the exposed portion of the upper surface of the at least one interconnection layer.

公开(公告)号：US20200381400A1

公开(公告)日：2020-12-03

申请号：US16751468

申请日：2020-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HEESEOK LEE ,  YUNHYEOK IM ,  JISOO HWANG

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/367 ,  H01L23/14 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package may include a first substrate, a second substrate at least partially surrounding the first substrate, the first substrate disposed in an opening penetrating the second substrate, and a semiconductor chip on the first substrate. The first substrate may be spaced apart from the second substrate in the opening, and a thickness of the first substrate may be less than a thickness of the second substrate.

公开(公告)号：US20200251455A1

公开(公告)日：2020-08-06

申请号：US16854971

申请日：2020-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUNHYEOK IM ,  KYOUNG-MIN LEE ,  KYUNGSOO LEE ,  HORANG JANG

IPC: H01L25/10 ,  H01L23/42 ,  H01L23/498 ,  H01L23/367 ,  H01L23/538 ,  H01L23/552

Abstract: A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interposed between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.

公开(公告)号：US20230207414A1

公开(公告)日：2023-06-29

申请号：US17952925

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSANG CHO ,  HEESEOK LEE ,  YUNHYEOK IM

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06568 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L24/05

Abstract: A semiconductor package includes a first interconnection structure, a first semiconductor chip disposed on the first interconnection structure and including a plurality of through-vias and first pads connected to the plurality of through-vias; a second semiconductor chip disposed on the first interconnection structure, including second pads electrically connected to the first pads, and having a size different from a size of the first semiconductor chip; a heat dissipation structure contacting and surrounding side surfaces of at least one of the first semiconductor chip and the second semiconductor chip, and including a material having higher thermal conductivity than a thermal conductivity of silicon; and an encapsulant surrounding side surfaces of the heat dissipating structure.

公开(公告)号：US20220328381A1

公开(公告)日：2022-10-13

申请号：US17850504

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HEESEOK LEE ,  YUNHYEOK IM

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

公开(公告)号：US20210296198A1

公开(公告)日：2021-09-23

申请号：US17030092

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUNHYEOK IM ,  YOUNGSANG CHO

IPC: H01L23/36 ,  H01L23/498

Abstract: A semiconductor module may include a substrate including a first region and a second region, a first chip mounted in the first region, a second chip and passive devices mounted in the second region, and a heat dissipation layer being in contact with a top surface of the first chip. The heat dissipation layer may be provided on top surfaces and side surfaces of the first chip, the second chip and the passive devices.

公开(公告)号：US20210272880A1

公开(公告)日：2021-09-02

申请号：US17016115

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HEESEOK LEE ,  YUNHYEOK IM

IPC: H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

公开(公告)号：US20190229100A1

公开(公告)日：2019-07-25

申请号：US16056709

申请日：2018-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUNHYEOK IM ,  KYOUNG-MIN LEE ,  KYUNGSOO LEE ,  HORANG JANG

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/367 ,  H01L23/42

Abstract: A semiconductor package includes a bottom package having a lower substrate and a lower semiconductor chip mounted on the lower substrate, an interposer substrate on the bottom package, a first top package and a second top package that are mounted on the interposer substrate, and a heat spreader that is interpose between the first top package and the second top package and separates the first and second top packages from each other. The heat spreader is adhered to the interposer substrate through a plurality of first connection terminals.