公开(公告)号：US09711530B1

公开(公告)日：2017-07-18

申请号：US15158954

申请日：2016-05-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke Ikawa ,  Kiyohiko Sakakibara ,  Eisuke Takii

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02598 ,  H01L28/00 ,  H01L29/511 ,  H01L29/518

Abstract: Threshold voltage shift due to programming of a neighboring memory element can be reduced or suppressed by forming a compositionally modulated charge storage layer in a three-dimensional memory device. The compositionally modulated charge storage layer can be formed by providing an oxygen-containing dielectric silicon compound layer outside a tunneling dielectric layer, and subsequently nitriding portions of the oxygen-containing dielectric silicon compound layer only at levels of the control gate electrodes. An alternating stack of sacrificial material layers and insulating layers can be employed to form a memory stack structure therethrough. After removal of the sacrificial material layers, a nitridation process can be performed to convert physically exposed portions of the oxygen-containing dielectric silicon compound layer into silicon nitride portions, which are vertically spaced from one another by remaining oxygen-containing dielectric silicon compound portions that have inferior charge trapping property to the silicon nitride portions.

公开(公告)号：US09812463B2

公开(公告)日：2017-11-07

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Fei Zhou ,  Somesh Peri ,  Masanori Tsutsumi ,  Keerti Shukla ,  Yusuke Ikawa ,  Kiyohiko Sakakibara ,  Eisuke Takii

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

公开(公告)号：US10355100B1

公开(公告)日：2019-07-16

申请号：US15982266

申请日：2018-05-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu Ueda ,  Tomoyuki Obu ,  Kazutaka Yoshizawa ,  Yasuyuki Aoki ,  Eisuke Takii ,  Akio Nishida

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/115 ,  H01L27/092 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11529

Abstract: A first field effect transistor and a second field effect transistor are formed on a substrate. A silicon nitride liner is formed over the first field effect transistor and the second field effect transistor. An upper portion of the silicon nitride liner is converted into a thermal silicon oxide liner. A lower portion of the silicon nitride liner remains as a silicon nitride material portion. A first portion of the thermal silicon oxide liner is removed from above the second field effect transistor, and a second portion of the thermal silicon oxide liner remains above the first field effect transistor. Selective presence of the silicon oxide liner provides differential stress within the channels of the first and second field effect transistors, which can be employed to optimize performance of different types of field effect transistors.