公开(公告)号：US20230328984A1

公开(公告)日：2023-10-12

申请号：US18060732

申请日：2022-12-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki FUJIMURA ,  Takashi KUDO ,  Shunsuke TAKUMA ,  Satoshi SHIMIZU

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory device includes at least one alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface; and one of the electrically conductive layers is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.

公开(公告)号：US20220344365A1

公开(公告)日：2022-10-27

申请号：US17237476

申请日：2021-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki FUJIMURA ,  Satoshi SHIMIZU ,  Takumi MORIYAMA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A plurality of arrays of memory opening fill structures is formed through the alternating stack. A plurality of dielectric plates is formed, which laterally surrounds a respective array of memory opening fill structures. Self-aligned drain-select-level isolation structures are formed between a respective neighboring pair of arrays of memory opening fill structures through gaps between neighboring pairs of the dielectric plates into a subset of layers within the alternating stack. Drain side select gate electrodes are provided from a divided subset of the spacer material layers.

公开(公告)号：US20240015963A1

公开(公告)日：2024-01-11

申请号：US17811145

申请日：2022-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tadashi NAKAMURA ,  Nobuyuki FUJIMURA

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers include word line electrically conductive layers and a first select-level electrically conductive layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. A vertical cross-sectional profile of an outer sidewall of the vertical semiconductor channel is straight throughout the word line electrically conductive layers and contains a lateral protrusion at a level of the first select-level electrically conductive layer.

公开(公告)号：US20240260267A1

公开(公告)日：2024-08-01

申请号：US18356919

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Naohiro HOSODA ,  Takumi MORIYAMA ,  Ryota SUZUKI ,  Takashi KUDO ,  Nobuyuki FUJIMURA

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A method of making a memory device includes forming an alternating stack of insulating layers and sacrificial material layers, where a silicon oxycarbide liner is interposed between a first sacrificial material layer and a first insulating layer, and the first sacrificial material layer is direct contact with a second insulating layer or a dielectric material layer composed of a silicon oxide material, forming a memory opening through the alternating stack, forming a memory opening fill structure in the memory opening, forming backside recesses by removing the sacrificial material layers selective to the silicon oxycarbide liner, and forming electrically conductive layers in the backside recesses.

公开(公告)号：US20240147723A1

公开(公告)日：2024-05-02

申请号：US18351181

申请日：2023-07-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoo OHAGA ,  Tadashi NAKAMURA ,  Takashi YUDA ,  Nobuyuki FUJIMURA ,  Hiroyuki OGAWA

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes source-level material layers including a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and the source contact layer, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel including an intrinsic or first conductivity type semiconductor material, a memory film surrounding the vertical semiconductor channel, and a conical source pedestal in contact with the source contact layer and in contact with a bottom surface of the vertical semiconductor channel, such that at least portion of the conical source pedestal includes a second conductivity type semiconductor material.