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公开(公告)号：US10367528B2
公开(公告)日：2019-07-30
申请号：US15179069
申请日：2016-06-10
摘要： In an illustrative example, a method includes receiving data to be processed in accordance with a convolutional low-density parity-check (CLDPC) code. The method also includes processing the data based on a parity check matrix associated with the CLDPC code. The parity check matrix includes a first portion and a second portion. The first portion includes a plurality of copies of a first sub-matrix that is associated with a first sub-code, and the second portion includes a copy of second sub-matrix that is associated with a second sub-code.
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公开(公告)号：US09947399B2
公开(公告)日：2018-04-17
申请号：US14669731
申请日：2015-03-26
发明人： Ariel Navon , Idan Alrod , Eran Sharon , Idan Goldenberg , Didi Gur
CPC分类号： G11C13/0069 , G06F11/1048 , G06F11/1056 , G06F11/1068 , G11C13/0033 , G11C13/004 , G11C13/0097 , G11C29/52 , G11C2013/0076 , G11C2013/0085
摘要： Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.
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3.发明申请公开(公告)号：US20180287634A1
公开(公告)日：2018-10-04
申请号：US15475602
申请日：2017-03-31
发明人： Rami Rom , Idan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , Idan Alrod , Stella Achtenberg
CPC分类号： H03M13/118 , G06F3/0619 , G06F3/0655 , G06F3/0688 , G06F11/10 , G06F11/1048 , H03M13/1102 , H03M13/1125 , H03M13/116 , H03M13/3715 , H03M13/616 , H03M13/6516 , H03M13/6566
摘要： A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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公开(公告)号：US10230395B2
公开(公告)日：2019-03-12
申请号：US15475638
申请日：2017-03-31
发明人： Rami Rom , Idan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , Idan Alrod , Stella Achtenberg
摘要： A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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公开(公告)号：US10063258B2
公开(公告)日：2018-08-28
申请号：US15265045
申请日：2016-09-14
发明人： Idan Goldenberg , Ishai Ilani , Alexander Bazarsky , Rami Rom
CPC分类号： H03M13/1154 , G06F11/10 , G06F11/1012 , G06F11/1052 , G06F11/106 , G06F11/1072 , G06F11/1076 , H03M13/1105 , H03M13/1108 , H03M13/353 , H03M13/3715 , H03M13/3723 , H03M13/612 , H03M13/6325
摘要： In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.
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6.发明授权公开(公告)号：US10355712B2
公开(公告)日：2019-07-16
申请号：US15475602
申请日：2017-03-31
发明人： Rami Rom , Idan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , Idan Alrod , Stella Achtenberg
摘要： A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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公开(公告)号：US10567001B2
公开(公告)日：2020-02-18
申请号：US16049069
申请日：2018-07-30
发明人： Idan Goldenberg , Ishai Ilani , Alexander Bazarsky , Rami Rom
摘要： In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.
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公开(公告)号：US10236909B2
公开(公告)日：2019-03-19
申请号：US15475666
申请日：2017-03-31
发明人： Rami Rom , Idan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , Idan Alrod , Stella Achtenberg
摘要： A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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公开(公告)号：US10218384B2
公开(公告)日：2019-02-26
申请号：US15366859
申请日：2016-12-01
发明人： Eran Sharon , Idan Goldenberg , Ishai Ilani , Idan Alrod , Yuri Ryabinin , Yan Dumchin , Mark Fiterman , Ran Zamir
摘要： A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.
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公开(公告)号：US10158380B2
公开(公告)日：2018-12-18
申请号：US15371167
申请日：2016-12-06
发明人： Eran Sharon , Alexander Bazarsky , Idan Goldenberg , Stella Achtenberg , Omer Fainzilber , Ran Zamir
摘要： A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.
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