公开(公告)号：US11355433B2

公开(公告)日：2022-06-07

申请号：US16674739

申请日：2019-11-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Derryl Allman ,  Jefferson W. Hall

IPC: H01L23/525 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor device having a fuse structure includes a region of semiconductor material having a major surface. A dielectric region is over the major surface. A first fuse terminal is over a first part of the dielectric region, a second fuse terminal is over a second part of the dielectric region and spaced apart from the first fuse terminal to provide a gap region, and a fuse body over a third part of the dielectric region interposed between and connected to the first fuse terminal and the second fuse terminal. A dummy structure is over the dielectric region in the gap region on a first side of the fuse body, the dummy structure spaced apart and electrically isolated from the fuse body, the first fuse terminal, and the second fuse terminal. The dummy structure is configured to reduce the presence of or reduce the effects of defects, such as cracks or voids that can emanate from the fuse structure.

公开(公告)号：US11088072B2

公开(公告)日：2021-08-10

申请号：US16576665

申请日：2019-09-19

Applicant: Semiconductor Components Industries, LLC

Inventor： Jefferson W. Hall ,  Gordon M. Grivna

IPC: H01L23/525 ,  G11C17/16 ,  G11C17/18 ,  H01L21/768 ,  H01L23/532 ,  H01L27/112

Abstract: A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.

公开(公告)号：US10811598B2

公开(公告)日：2020-10-20

申请号：US16794721

申请日：2020-02-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jefferson W. Hall ,  Michael J. Seddon ,  Yenting Wen

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R31/28 ,  G01R15/18 ,  G01R15/20 ,  G01R19/00

Abstract: A sensor package includes a semiconductor die including at least one current sensor. The semiconductor die includes a first pass through hole extending from one side of the semiconductor die to an opposite side of the semiconductor die. The semiconductor package further includes a second pass through hole extending from one side of the sensor package to an opposite side of the sensor package. The second pass through hole is aligned with the first pass through hole and is configured to receive a current-carrying conductor. The at least one current sensor senses current flow in the current-carrying conductor received in the second pass through hole. An end of the current-carrying conductor is coupled to a terminal on a circuit board in the sensor package.

公开(公告)号：US20190273094A1

公开(公告)日：2019-09-05

申请号：US16415164

申请日：2019-05-17

Applicant: Semiconductor Components Industries, LLC

Inventor： Jefferson W. Hall ,  Gordon M. Grivna

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.

公开(公告)号：US09793002B2

公开(公告)日：2017-10-17

申请号：US15073121

申请日：2016-03-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jefferson W. Hall

IPC: G11C17/18 ,  G11C17/16 ,  H01L27/112 ,  H01L27/105 ,  H01L23/522 ,  G11C5/14

CPC classification number: G11C17/18 ,  G11C5/147 ,  G11C17/16 ,  H01L23/5228 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11293 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.

公开(公告)号：US09331065B2

公开(公告)日：2016-05-03

申请号：US14803365

申请日：2015-07-20

Applicant: Semiconductor Components Industries, LLC

Inventor： Gordon M. Grivna ,  Jefferson W. Hall ,  Mohammed Tanvir Quddus

IPC: H01L29/06 ,  H01L27/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762 ,  H01L27/06 ,  H01L29/872 ,  H01L29/40

CPC classification number: H01L27/0255 ,  H01L21/76224 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1037 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/402 ,  H01L29/42364 ,  H01L29/66143 ,  H01L29/7806 ,  H01L29/8725

Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.

公开(公告)号：US20150279478A1

公开(公告)日：2015-10-01

申请号：US14225272

申请日：2014-03-25

Applicant: Semiconductor Components Industries, LLC

Inventor： Jefferson W. Hall

IPC: G11C17/18 ,  H01L27/112 ,  H01L27/105 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C5/147 ,  G11C17/16 ,  H01L23/5228 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11293 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.

Abstract translation: 在一个实施例中，编程电路被配置为通过使用非硅化物编程元件来形成硅化物熔丝元件的编程电流。

公开(公告)号：US12230559B2

公开(公告)日：2025-02-18

申请号：US18329347

申请日：2023-06-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. Carney ,  Jefferson W. Hall ,  Michael J. Seddon

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L27/146 ,  H01L29/08 ,  H02M3/158 ,  H01L23/14 ,  H01L23/15 ,  H01L23/367

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

公开(公告)号：US11258374B2

公开(公告)日：2022-02-22

申请号：US16547793

申请日：2019-08-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jefferson W. Hall ,  Ajay Karthik Hari

IPC: H02M7/5387 ,  H02M1/08 ,  G05B13/02 ,  H02J13/00 ,  G06N3/08 ,  G06F1/26 ,  G06F1/32 ,  H02M1/00

Abstract: According to an aspect, a power supply system includes a power stage, a power supply controller configured to control operations of the power stage, a metering circuit configured to sense measured conditions of the power stage, and a system performance controller configured to be coupled to the power supply controller and the metering circuit. The system performance controller is configured to set or adjust a control parameter for the power stage based on standby power of the power stage. The system performance controller includes a standby power computation circuit configured to compute the standby power of the power stage based on the measured conditions, and a control manipulation module configured to modify the control parameter until the standby power achieves a threshold condition.

公开(公告)号：US10804296B2

公开(公告)日：2020-10-13

申请号：US16415164

申请日：2019-05-17

Applicant: Semiconductor Components Industries, LLC

Inventor： Jefferson W. Hall ,  Gordon M. Grivna

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L29/40 ,  H01L29/78

Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.