公开(公告)号：US11776870B2

公开(公告)日：2023-10-03

申请号：US16744378

申请日：2020-01-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino Mercado Tolentino ,  Shutesh Krishnan ,  Francis J. Carney

IPC: H01L23/373 ,  B22F7/06 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/3735 ,  B22F7/064 ,  H01L21/4882 ,  B22F2301/10 ,  H01L24/09 ,  H01L24/29

Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.

公开(公告)号：US10930604B2

公开(公告)日：2021-02-23

申请号：US15939843

申请日：2018-03-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Nurul Nadiah Manap ,  Shutesh Krishnan ,  Soon Wei Wang

IPC: H01L25/065 ,  H01L23/00

Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.

公开(公告)号：US10319639B2

公开(公告)日：2019-06-11

申请号：US15679664

申请日：2017-08-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shutesh Krishnan ,  Sw Wang ,  CH Chew ,  How Kiat Liew ,  Fui Fui Tan

IPC: H01L21/78 ,  H01L21/00 ,  H01L21/306 ,  H01L23/482

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

公开(公告)号：US20170352635A1

公开(公告)日：2017-12-07

申请号：US15663802

申请日：2017-07-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Shutesh Krishnan ,  Yun Sung Won

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/27 ,  H01L23/49513 ,  H01L23/49524 ,  H01L24/29 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/29 ,  H01L2224/29006 ,  H01L2224/29101 ,  H01L2224/29199 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/838 ,  H01L2224/8384 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/37099

Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

公开(公告)号：US12170239B2

公开(公告)日：2024-12-17

申请号：US18469615

申请日：2023-09-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino Mercado Tolentino ,  Shutesh Krishnan ,  Francis J. Carney

IPC: H01L23/373 ,  B22F7/06 ,  H01L21/48 ,  H01L23/00 ,  H01L23/473 ,  H05K7/20

Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.

公开(公告)号：US11942369B2

公开(公告)日：2024-03-26

申请号：US16942916

申请日：2020-07-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shutesh Krishnan ,  Sw Wei Wang ,  Ch Chew ,  How Kiat Liew ,  Fui Fui Tan

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/482 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L29/06

CPC classification number: H01L21/78 ,  H01L21/306 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/482 ,  H01L29/0657

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

公开(公告)号：US10763173B2

公开(公告)日：2020-09-01

申请号：US16395822

申请日：2019-04-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shutesh Krishnan ,  Sw Wei Wang ,  Ch Chew ,  How Kiat Liew ,  Fui Fui Tan

IPC: H01L21/78 ,  H01L21/00 ,  H01L21/306 ,  H01L23/482 ,  H01L21/56 ,  H01L23/31 ,  H01L29/06

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

公开(公告)号：US09780059B2

公开(公告)日：2017-10-03

申请号：US14339524

申请日：2014-07-24

Applicant: Semiconductor Components Industries, LLC

Inventor： Shutesh Krishnan ,  Yun Sung Won

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L24/27 ,  H01L23/49513 ,  H01L23/49524 ,  H01L24/16 ,  H01L24/29 ,  H01L24/36 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/29 ,  H01L2224/29006 ,  H01L2224/29101 ,  H01L2224/29199 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/8184 ,  H01L2224/83048 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/838 ,  H01L2224/8384 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/37099 ,  H01L2224/05599

Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

公开(公告)号：US12160060B2

公开(公告)日：2024-12-03

申请号：US18298148

申请日：2023-04-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino Mercado Tolentino ,  Dennis Cadiz Yborde ,  Shutesh Krishnan ,  Pui Leng Low

IPC: H01R12/73 ,  H01L23/498

Abstract: A system for attaching a terminal pin to a circuit trace on an electronic substrate. The system includes a sonotrode and a stage for holding the electronic substrate. The sonotrode is configured to direct ultrasound energy to a base region of the terminal pin placed on the circuit trace to weld the base region to the circuit trace. The system further includes a three-dimensional positioner coupled to the sonotrode. The three-dimensional positioner is configured to drive the sonotrode to lift the terminal pin from a rack and to place the terminal pin on the electronic substrate.

公开(公告)号：US11830856B2

公开(公告)日：2023-11-28

申请号：US16745762

申请日：2020-01-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong Chew ,  Erik Nino Tolentino ,  Vemmond Jeng Hung Ng ,  Shutesh Krishnan

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/373 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/072 ,  H01L23/3735 ,  H01L24/40 ,  H01L24/84 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/4001 ,  H01L2224/4052 ,  H01L2224/40137 ,  H01L2224/40991 ,  H01L2224/8484 ,  H01L2224/84931 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0503 ,  H01L2924/1203 ,  H01L2924/13055

Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.