公开(公告)号：US20180005951A1

公开(公告)日：2018-01-04

申请号：US15448008

申请日：2017-03-02

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Shinzo ISHIBE

IPC: H01L23/532 ,  H01L23/528 ,  H01L29/739 ,  H01L29/861 ,  H01L23/00

Abstract: A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

公开(公告)号：US20240404879A1

公开(公告)日：2024-12-05

申请号：US18492867

申请日：2023-10-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Shinzo ISHIBE

IPC: H01L21/768 ,  C23C18/30 ,  C23C18/42 ,  H01L21/683

Abstract: Implementations of a method of electroless deposition may include providing a semiconductor substrate including a first largest planar surface and a second largest planar surface; forming a backmetal layer on the second largest planar surface; attaching a tape over the backmetal layer; and electroless depositing a metal layer on a pad included on the first largest planar surface. The method may include, after electroless depositing, removing the tape; and after removing the tape, baking the semiconductor substrate.

公开(公告)号：US20240290736A1

公开(公告)日：2024-08-29

申请号：US18175079

申请日：2023-02-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shinzo ISHIBE ,  Takashi NOMA

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664

Abstract: Implementations of a method of forming an over pad metallization structure may include providing a semiconductor substrate including a plurality of copper pads on a first side of the semiconductor substrate; electroless plating an over pad metallization including nickel, palladium, and gold onto each copper pad of the plurality of copper pads; and patterning a layer of photoresist onto the over pad metallization of each copper pad of the plurality of copper pads. The method may include forming a mold compound over the plurality of copper pads, the over pad metallization, and the layer of photoresist of each copper pad; removing a portion of the mold compound and a portion of the layer of photoresist of each copper pad of the plurality of copper pads; and removing the layer of photoresist to expose the over pad metallization of each copper pad of the plurality of copper pads.

公开(公告)号：US20240128215A1

公开(公告)日：2024-04-18

申请号：US18485565

申请日：2023-10-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Shinzo ISHIBE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/45 ,  H01L24/85 ,  H01L24/13 ,  H01L24/73 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/11 ,  H01L2224/131 ,  H01L2224/45124 ,  H01L2224/73207 ,  H01L2224/8584

Abstract: A device may include an insulating layer disposed on a frontside of a semiconductor layer, and may include a first conductive contact disposed in a first opening in the insulating layer. The device may include a second conductive contact disposed in a second opening in the insulating layer, and may include a stacked conductive layer disposed on the first conductive contact and excluded from the second conductive contact.

公开(公告)号：US20190148306A1

公开(公告)日：2019-05-16

申请号：US16229186

申请日：2018-12-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Shinzo ISHIBE ,  Kazuyuki SUTO

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/265 ,  H01L29/861 ,  H01L29/739 ,  H01L21/324 ,  H01L23/528 ,  H01L21/22 ,  H01L21/28 ,  H01L23/482 ,  H01L21/304

Abstract: Implementations of a semiconductor device may include: a silicon substrate including a first side and a second side. The second side of the substrate may include an active area. The device may include a metal stack including: a back metallization on the first side of the substrate, an electroplated metal layer on the back metallization; and an evaporated gold metal layer on the electroplated metal layer.