公开(公告)号：US20240323567A1

公开(公告)日：2024-09-26

申请号：US18460587

申请日：2023-09-04

Applicant: SK hynix Inc.

Inventor： Jung Soon SHIN ,  Seong Hee PARK ,  Ki Young KIM ,  Jong Eun KIM

IPC: H04N25/771 ,  G06F17/16 ,  H04N25/78

CPC classification number: H04N25/771 ,  G06F17/16 ,  H04N25/78 ,  H01L27/14634

Abstract: Disclosed is an image sensor including a plurality of column lines, a plurality of pixels coupled to the plurality of column lines, and configured to output a plurality of pixel signals to the plurality of column lines in response to first control signals, and a plurality of memory cells coupled to the plurality of column lines, and configured to output a plurality of convolution signals, in which a plurality of data signals are reflected in the plurality of pixel signals, to the plurality of column lines in response to second control signals.

公开(公告)号：US20210279132A1

公开(公告)日：2021-09-09

申请号：US16945068

申请日：2020-07-31

Applicant: SK hynix Inc.

Inventor： Ki Young KIM

IPC: G06F11/10 ,  G06F11/16 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0882

Abstract: The present technology relates to an electronic device. A memory controller controls a memory device such that a life of the memory device is increased. The memory controller that controls the memory device includes a flash translation layer configured to generate a device health descriptor based on device information received from the memory device, and a bad block controller configured to generate a bad block table based on bad block information received from the memory device, and generate recycling information for recycling pages in bad blocks recorded in the bad block table based on the device health descriptor.

公开(公告)号：US20140291840A1

公开(公告)日：2014-10-02

申请号：US14305527

申请日：2014-06-16

Applicant: SK hynix Inc.

Inventor： Jin Ho BAE ,  Ki Young KIM ,  Jong Hyun NAM

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/49816 ,  H01L24/09 ,  H01L24/16 ,  H01L24/18 ,  H01L24/20 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/17104 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.

Abstract translation: 叠层半导体芯片包括支撑半导体芯片模块的主衬底，其中半导体模块包括至少两个次半导体芯片模块，每个子半导体芯片模块具有嵌入第一半导体芯片的子衬底，并且至少两个第二半导体芯片堆叠在 副底物。

公开(公告)号：US20240256457A1

公开(公告)日：2024-08-01

申请号：US18457352

申请日：2023-08-29

Applicant: SK hynix Inc.

Inventor： Ki Young KIM

IPC: G06F12/0862 ,  G06F12/02

CPC classification number: G06F12/0862 ,  G06F12/0292 ,  G06F2212/2022

Abstract: Provided are a storage device capable of reducing formation time of map data required for an HPB read operation and stored in a host, and an operation method thereof. The operation method of a memory controller includes performing a host performance booster (HPB) read operation of reading data from a memory in response to a read request from a first external device using map data stored in a plurality of map data areas of a volatile memory area of the first external device, obtaining a usage frequency for each of the plurality of map data areas, and storing information on at least one map data area with a highest usage frequency in an HPB priority buffer configured as a non-volatile memory.

公开(公告)号：US20230096854A1

公开(公告)日：2023-03-30

申请号：US17705068

申请日：2022-03-25

Applicant: SK hynix Inc.

Inventor： Young Jae JIN ,  Ki Young KIM ,  Sang Eun JE

IPC: G06N3/063 ,  G06N3/04 ,  G06K9/62

Abstract: A data processing system includes a controller and a computation device. The controller receives a request for processing a neural network computation from a host, the request including an input feature map and a weight filter. The computation device includes a storage unit allocated to each of integration groups, and performs a convolution operation on the input feature map and the weight filter, sequentially outputs pooling elements as a result of the convolution operation, and performs a pooling operation on the pooling elements. The pooling elements corresponds to each integration group. The computation device performs the pooling operation by integrating a pooling value read from the storage unit and each of the pooling elements into a single value and updating the pooling value stored in the storage unit with a result of the integrating. The integrating and the updating are repeated until all of the pooling elements are integrated.

公开(公告)号：US20140015144A1

公开(公告)日：2014-01-16

申请号：US13690771

申请日：2012-11-30

Applicant: SK HYNIX INC.

Inventor： Ki Young KIM ,  Myung Gun PARK

IPC: H01L23/538 ,  H01L23/495

CPC classification number: H01L23/5384 ,  H01L23/3128 ,  H01L23/495 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/73 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A multi-chip package includes a main substrate; a plurality of first semiconductor chips stacked on an upper surface of the main substrate and having bonding pads which are electrically connected with the main substrate; and a semiconductor package attached to side surfaces of the stacked first semiconductor chips and electrically connected with the main substrate.

Abstract translation: 多芯片封装包括主基板; 多个第一半导体芯片，堆叠在主基板的上表面上并具有与主基板电连接的接合焊盘; 以及附接到堆叠的第一半导体芯片的侧表面并与主基板电连接的半导体封装。

公开(公告)号：US20230113627A1

公开(公告)日：2023-04-13

申请号：US17703873

申请日：2022-03-24

Applicant: SK hynix Inc.

Inventor： Ki Young KIM ,  Sang Eun JE

IPC: G06N3/063 ,  H03M1/36 ,  G11C13/00 ,  G06F7/544

Abstract: Provided herein may be an electronic device. The electronic device may include a crossbar array including a plurality of first memory cells, a plurality of second memory cells, a plurality of row lines, a plurality of first column lines and a second column line, and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage. Each of the plurality of analog-to-digital converters determines a maximum value allowed to the analog signal voltage based on the reference voltage.

公开(公告)号：US20210255978A1

公开(公告)日：2021-08-19

申请号：US16997256

申请日：2020-08-19

Applicant: SK hynix Inc.

Inventor： Ki Young KIM

IPC: G06F13/372 ,  G06F13/374 ,  G06F9/48 ,  G06F9/38 ,  G06F1/14

Abstract: A data processing apparatus includes a master device configured to transmit commands for destinations, a slave device including a plurality of command processing regions respectively corresponding to the destinations, and a controller configured to relay communication between the master device and the slave device. The controller assigns time stamp value to the commands as an initial value when the commands was received by the controller and increment the time stamp value every command arbitration cycle, selects a command having a largest time stamp value among the commands in a tournament manner by comparing commands having different destinations every command arbitration cycle, stores a command selection history of each comparison of commands, selects the command based on a command selection history corresponding to the compared commands when respective time stamp values of the compared commands are the same or substantially the same as each other.

公开(公告)号：US20240241656A1

公开(公告)日：2024-07-18

申请号：US18468742

申请日：2023-09-18

Applicant: SK hynix Inc.

Inventor： Ki Young KIM

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory system which includes a nonvolatile memory device configured to store a mapping table that includes a plurality of map segments each having mapping information between a logical address and a physical address; and a controller configured to: transfer the mapping information to a host through a host performance booster (HPB) operation based on a mode, which is selected by the host from a host control mode and a device control mode, and selectively request the host to change the mode between the host control mode and the device control mode based on a ratio of a read request with a physical address to all read requests, which are transferred from the host.

公开(公告)号：US20220385295A1

公开(公告)日：2022-12-01

申请号：US17521603

申请日：2021-11-08

Applicant: SK hynix Inc.

Inventor： Sang Eun JE ,  Ki Young KIM

IPC: H03M1/00 ,  G06N3/063 ,  G11C13/00

Abstract: An electronic device includes analog-to-digital converters each configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal, an analog input signal generator configured to generate analog input signals provided to each analog-to-digital converter based on input voltages and weight data, an input signal distribution information generator configured to generate input signal distribution information indicating a distribution of the analog input signals for each of the analog-to-digital converters, an analog-to-digital converter group classifier configured to classify the analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information, and an analog-to-digital converter input range optimizer configured to determine an input range of each first analog-to-digital converter group based on the input signal distribution information, and each analog-to-digital converter is configured to operate according to an input range of a corresponding first analog-to-digital converter groups.