-
公开(公告)号:US11191151B2
公开(公告)日:2021-11-30
申请号:US16562082
申请日:2019-09-05
Applicant: SK hynix Inc.
Inventor: Kyu Yong Choi , Jin Ho Bae , Yu Jeong Choe
Abstract: A device may include a substrate having a first surface and a second surface, a first conductive terminal disposed over the first surface, a second conductive terminal spaced apart from the first conductive terminal in a first direction and disposed over the first surface, a first conductive auxiliary pattern disposed below the first conductive terminal and overlapping with the first conductive terminal, the first conductive auxiliary pattern being coupled to the second conductive terminal, and a second conductive auxiliary pattern disposed below the second conductive terminal and overlapping with the second conducive terminal, the second conductive auxiliary pattern being coupled to the first conductive terminal.
-
公开(公告)号:US09184147B2
公开(公告)日:2015-11-10
申请号:US14305527
申请日:2014-06-16
Applicant: SK hynix Inc.
Inventor: Jin Ho Bae , Ki Young Kim , Jong Hyun Nam
IPC: H01L23/02 , H01L23/48 , H01L23/28 , H01L23/52 , H01L29/40 , H05K7/00 , H05K1/18 , H01L23/00 , H01L25/065 , H01L23/498
CPC classification number: H01L24/17 , H01L23/49816 , H01L24/09 , H01L24/16 , H01L24/18 , H01L24/20 , H01L24/29 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2224/17104 , H01L2224/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49113 , H01L2224/73265 , H01L2224/73267 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
Abstract: A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.
Abstract translation: 叠层半导体芯片包括支撑半导体芯片模块的主衬底,其中半导体模块包括至少两个次半导体芯片模块,每个子半导体芯片模块具有嵌入第一半导体芯片的子衬底,并且至少两个第二半导体芯片堆叠在 副底物。
-
公开(公告)号:US08653660B2
公开(公告)日:2014-02-18
申请号:US13778413
申请日:2013-02-27
Applicant: SK hynix Inc.
Inventor: Jin Ho Bae
IPC: H01L23/48
CPC classification number: H01L23/498 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L29/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83194 , H01L2225/0651 , H01L2225/06555 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/10158 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.
Abstract translation: 半导体器件包括具有上表面,下表面,第一侧和第二侧的半导体衬底,其中下表面具有斜面,使得第一侧比第二侧厚;以及电路图案,包括接合 衬垫在半导体衬底的上表面上。
-
4.
公开(公告)号:US09412716B2
公开(公告)日:2016-08-09
申请号:US14284637
申请日:2014-05-22
Applicant: SK hynix Inc.
Inventor: Jin Ho Bae , Qwan Ho Chung , Seong Kweon Ha , Jong Hyun Kim , Bok Gyu Min , Jae Won Shin
CPC classification number: H01L24/85 , H01L21/481 , H01L22/32 , H01L23/12 , H01L23/49838 , H01L23/49894 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/73265 , H01L2224/85 , H01L2924/00014 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
Abstract: A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each other with the intervention of saw lines, first ground connection pads formed on the respective unit substrates, each of the first ground connection pads being electrically coupled with the first connection pad over the respective unit substrates, second ground connection pads formed on the saw line on the first surface side of the unit substrates and electrically isolated from the unit substrates, and test wiring formed on the saw line, the test wiring being electrically isolated from the unit substrates and electrically coupled with the second ground connection pads; and attaching semiconductor chips onto the respective unit substrates.
Abstract translation: 一种制造半导体封装的方法,包括:形成包括多个单元基板的带状基板,每个单元基板在单元基板的第一表面上设置有第一连接焊盘和第二连接焊盘,并且每个单元基板被电气和物理隔离 通过锯线的干预,形成在各个单元基板上的第一接地连接焊盘,每个第一接地连接焊盘与相应的单元基板上的第一连接焊盘电耦合,形成在锯上的第二接地连接焊盘 在单元基板的第一表面侧上并且与单元基板电隔离,以及形成在锯线上的测试布线,测试布线与单元基板电隔离并与第二接地连接焊盘电耦合; 以及将半导体芯片附接到各个单元基板上。
-
公开(公告)号:US09343439B2
公开(公告)日:2016-05-17
申请号:US14884864
申请日:2015-10-16
Applicant: SK hynix Inc.
Inventor: Jin Ho Bae , Han Jun Bae
CPC classification number: H01L25/0657 , H01L23/3121 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/04042 , H01L2224/05548 , H01L2224/05553 , H01L2224/06135 , H01L2224/24145 , H01L2224/24146 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73217 , H01L2224/73227 , H01L2224/73265 , H01L2224/92135 , H01L2224/92164 , H01L2224/92244 , H01L2224/92247 , H01L2225/0651 , H01L2225/06524 , H01L2225/06551 , H01L2225/06568 , H01L2924/1434 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.
-
公开(公告)号:US09196607B2
公开(公告)日:2015-11-24
申请号:US14082441
申请日:2013-11-18
Applicant: SK hynix Inc.
Inventor: Jin Ho Bae , Han Jun Bae
CPC classification number: H01L25/0657 , H01L23/3121 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/04042 , H01L2224/05548 , H01L2224/05553 , H01L2224/06135 , H01L2224/24145 , H01L2224/24146 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2224/73217 , H01L2224/73227 , H01L2224/73265 , H01L2224/92135 , H01L2224/92164 , H01L2224/92244 , H01L2224/92247 , H01L2225/0651 , H01L2225/06524 , H01L2225/06551 , H01L2225/06568 , H01L2924/1434 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
Abstract: A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.
Abstract translation: 堆叠封装包括具有连接端子的基板和在基板上的第一芯片。 第一芯片在其边缘上具有第一连接器。 第二芯片堆叠在第一芯片上以暴露第一连接器的外部部分。 第二芯片在其边缘上具有第二连接器。 连接构件将第一连接器的暴露的外部部分连接到连接端子。 将第一连接器的暴露的外部部分连接到第二连接器的侧壁互连器。 侧壁互连器从第一连接器的暴露的外部部分延伸到第二芯片的侧壁以覆盖第二连接器。
-
-
-
-
-