公开(公告)号：US11664343B2

公开(公告)日：2023-05-30

申请号：US17222505

申请日：2021-04-05

Applicant: SK hynix Inc.

Inventor： Jong Hyun Kim

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/48 ,  H01L24/05 ,  H01L24/85 ,  H01L25/18 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/02141 ,  H01L2224/04042 ,  H01L2224/05541 ,  H01L2224/05553 ,  H01L2224/05558 ,  H01L2224/06135 ,  H01L2224/4846 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/48482 ,  H01L2224/49112 ,  H01L2224/85051

Abstract: A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k−1th semiconductor chip when k is 1.

公开(公告)号：US09455230B1

公开(公告)日：2016-09-27

申请号：US14878717

申请日：2015-10-08

Applicant: SK hynix Inc.

Inventor： Yeon Ji Park ,  Hyeon Ji Baek ,  Ki Yong Lee ,  Jong Hyun Kim

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/293 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip electrically connected to a substrate, and a molding part including first molding members and second molding members arranged in an alternating pattern. The first molding members have a first physical flexibility which is different from a second physical flexibility of the second molding members.

Abstract translation: 半导体封装包括电连接到基板的半导体芯片，以及包括第一模制构件和以交替模式布置的第二模制构件的模制部件。 第一模制构件具有与第二模制构件的第二物理柔性不同的第一物理柔性。

公开(公告)号：US12142592B2

公开(公告)日：2024-11-12

申请号：US18303300

申请日：2023-04-19

Applicant: SK hynix Inc.

Inventor： Jong Hyun Kim

IPC: H01L23/00 ,  H01L25/18

Abstract: A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k+1th semiconductor chip when k is 1.

公开(公告)号：US09412716B2

公开(公告)日：2016-08-09

申请号：US14284637

申请日：2014-05-22

Applicant: SK hynix Inc.

Inventor： Jin Ho Bae ,  Qwan Ho Chung ,  Seong Kweon Ha ,  Jong Hyun Kim ,  Bok Gyu Min ,  Jae Won Shin

IPC: H01L23/34 ,  H01L23/00 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H01L21/66

CPC classification number: H01L24/85 ,  H01L21/481 ,  H01L22/32 ,  H01L23/12 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor package includes: forming a strip substrate including a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each other with the intervention of saw lines, first ground connection pads formed on the respective unit substrates, each of the first ground connection pads being electrically coupled with the first connection pad over the respective unit substrates, second ground connection pads formed on the saw line on the first surface side of the unit substrates and electrically isolated from the unit substrates, and test wiring formed on the saw line, the test wiring being electrically isolated from the unit substrates and electrically coupled with the second ground connection pads; and attaching semiconductor chips onto the respective unit substrates.

Abstract translation: 一种制造半导体封装的方法，包括：形成包括多个单元基板的带状基板，每个单元基板在单元基板的第一表面上设置有第一连接焊盘和第二连接焊盘，并且每个单元基板被电气和物理隔离 通过锯线的干预，形成在各个单元基板上的第一接地连接焊盘，每个第一接地连接焊盘与相应的单元基板上的第一连接焊盘电耦合，形成在锯上的第二接地连接焊盘 在单元基板的第一表面侧上并且与单元基板电隔离，以及形成在锯线上的测试布线，测试布线与单元基板电隔离并与第二接地连接焊盘电耦合; 以及将半导体芯片附接到各个单元基板上。

公开(公告)号：US09208827B2

公开(公告)日：2015-12-08

申请号：US14526802

申请日：2014-10-29

Applicant: SK hynix Inc.

Inventor： Ki Yong Lee ,  Jong Hyun Kim ,  Sang Hwan Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/02 ,  G11C5/02 ,  H01L25/065 ,  H01L23/00 ,  G11C7/14 ,  H01L23/525 ,  G11C7/10 ,  G11C5/14 ,  G11C29/12

CPC classification number: G11C5/025 ,  G11C5/14 ,  G11C7/1057 ,  G11C7/1063 ,  G11C7/109 ,  G11C7/14 ,  G11C7/20 ,  G11C29/1201 ,  G11C2207/105 ,  H01L23/5256 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0901 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09515 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48106 ,  H01L2224/48147 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.

Abstract translation: 半导体堆叠封装可以包括形成有多个耦合焊盘的衬底，堆叠在衬底上的多个半导体芯片。 半导体堆叠封装还可以包括设置在每个半导体芯片上的第一电路单元，并且通过焊盘介质与耦合焊盘电连接。 半导体堆叠封装可以包括设置在每个半导体芯片上并与耦合焊盘电连接的第二电路单元，设置在每个半导体芯片上并对应于第二电路单元的连接焊盘以及耦合在第二电路单元 和连接垫。 半导体堆叠封装还可以包括电连接接合焊盘和耦合焊盘的接合线。

公开(公告)号：US09275959B2

公开(公告)日：2016-03-01

申请号：US14876752

申请日：2015-10-06

Applicant: SK hynix Inc.

Inventor： Hyung Ju Choi ,  Jong Hyun Kim

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L23/60

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/60 ,  H01L24/97 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15184 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate.

Abstract translation: 提供半导体封装。 在一些实施例中，半导体封装包括衬底，第一接地线包括沿着衬底的边缘设置的第一内部接地线和在第一内部接地线和衬底的侧壁之间的多个第一延伸接地线， 所述基板，设置在所述基板上以覆盖所述芯片的模制构件以及覆盖所述模制构件的电磁干扰（EMI）屏蔽层，所述EMI屏蔽层沿着所述基板的侧壁延伸并且接触所述多个第一 延长地线。 多个第一延伸接地线包括在基板的侧壁处露出的端部。

公开(公告)号：US09070691B2

公开(公告)日：2015-06-30

申请号：US14341288

申请日：2014-07-25

Applicant: SK HYNIX INC.

Inventor： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04 ,  H01L29/40 ,  H01L23/538 ,  H01L21/48 ,  H01L21/673 ,  H01L23/32 ,  H01L25/10 ,  H01L25/11 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

Abstract translation: 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 A至半导体芯片设置在第一区域中并与各布线电连接，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。

公开(公告)号：US09875990B2

公开(公告)日：2018-01-23

申请号：US14994235

申请日：2016-01-13

Applicant: SK hynix Inc.

Inventor： Hyung Ju Choi ,  Ki Yong Lee ,  Jong Hyun Kim ,  Hyoung Min Im

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.

公开(公告)号：US09589905B2

公开(公告)日：2017-03-07

申请号：US14245967

申请日：2014-04-04

Applicant: SK HYNIX INC.

Inventor： Hyung Ju Choi ,  Jong Hyun Kim

IPC: H01L23/552 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L22/32 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a substrate, a chip disposed over a top surface of the substrate, an electromagnetic interference (EMI) shielding layer disposed over the substrate such that the EMI shielding layer surrounds the chip, a ground pad disposed in the substrate to contact a bottom surface of the substrate, and a test pad disposed in the substrate to contact the bottom surface of the substrate and spaced apart from the ground pad. A method of testing the semiconductor package is performed using a loop circuit to which a current is applied, the loop circuit being formed by electrically coupling the ground pad, the EMI shielding layer, and the test pad.

Abstract translation: 半导体封装包括衬底，设置在衬底的顶表面上的芯片，设置在衬底上的电磁干扰（EMI）屏蔽层，使得EMI屏蔽层围绕芯片，设置在衬底中以接触衬底的接地焊盘 衬底的底表面和设置在衬底中以与衬底的底表面接触并与接地垫间隔开的测试焊盘。 使用施加了电流的环路电路来执行测试半导体封装的方法，该环路电路通过电耦合接地焊盘，EMI屏蔽层和测试焊盘而形成。

公开(公告)号：US09502378B1

公开(公告)日：2016-11-22

申请号：US14938322

申请日：2015-11-11

Applicant: SK hynix Inc.

Inventor： Ki Yong Lee ,  Jong Hyun Kim ,  Hyung Ju Choi

IPC: G01R31/26 ,  H01L21/66 ,  H01L23/00 ,  H05K1/11 ,  H05K1/02 ,  G01R31/28

CPC classification number: H01L24/85 ,  G01R31/2806 ,  G01R31/44 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/85186 ,  H01L2224/859 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15184 ,  H05K1/0268 ,  H05K3/0097 ,  H05K2201/09545 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85399

Abstract: A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.

Abstract translation: 提供一种半导体封装的制造方法。 该方法包括提供具有多个单元基板区域的带状基板，所述单元基板区域通过外围区域彼此间隔开并具有盲孔，设置在周边区域中的外围导电图案层，以及连接图案层，电连接盲孔 通孔到外围导电图案层。 半导体芯片分别设置在多个单元基板区域上。 导电线被形成为将设置在多个单元基板区域上的连接焊盘电连接到设置在半导体芯片上的接合焊盘。 连接焊盘电连接到盲孔，并且形成导线包括通过单元基板区域执行用于确认在每个导线和外围导电图案层之间流动的电流的测试。