公开(公告)号：US10854288B2

公开(公告)日：2020-12-01

申请号：US16206901

申请日：2018-11-30

申请人： SK hynix Inc.

发明人： Jin Su Park

IPC分类号： G11C11/34 ,  G11C13/00 ,  G11C5/14

摘要： A semiconductor memory apparatus includes an access line control circuit. The access line control circuit applies a selected bias voltage to a selected access line coupled with a target memory cell and applies a first unselected bias voltage to an unselected access line adjacent to the selected access line. A second unselected bias voltage is applied to an unselected access line not adjacent to the selected access line.

公开(公告)号：US10817222B2

公开(公告)日：2020-10-27

申请号：US16289907

申请日：2019-03-01

申请人： SK hynix Inc.

发明人： Seok Joon Kang ,  Jin Su Park ,  Ho Seok Em

IPC分类号： G06F11/07 ,  G06F3/06 ,  G11C13/00

摘要： A semiconductor system may include a memory controller and a non-volatile memory apparatus. The memory controller may generate a recovery command signal by measuring a power off time of the non-volatile memory apparatus. The non-volatile memory apparatus may perform a drift recovery operation based on the recovery command signal.

公开(公告)号：US09761287B2

公开(公告)日：2017-09-12

申请号：US15291725

申请日：2016-10-12

申请人： SK hynix Inc.

发明人： Min Gi Hong ,  Jin Su Park

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C7/20 ,  G11C8/10

CPC分类号： G11C7/1087 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

公开(公告)号：US20240345760A1

公开(公告)日：2024-10-17

申请号：US18465071

申请日：2023-09-11

申请人： SK hynix Inc.

发明人： Chan Hee LEE ,  Jin Su Park ,  Myeong Jae Kim

IPC分类号： G06F3/06

CPC分类号： G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

摘要： Embodiments of the present disclosure may provide measures for performing tuning of signals transmitted and received by a storage device, by providing a test signal provided by a test signal generator included in the storage device to a loopback path between a transmission block and a reception block of the storage device. By easily performing signal tuning of the storage device and preventing or reducing distortion of signals transmitted and received by the storage device, operational performance of the storage device may be improved.

公开(公告)号：US10861505B2

公开(公告)日：2020-12-08

申请号：US16289981

申请日：2019-03-01

申请人： SK hynix Inc.

发明人： Seok Joon Kang ,  Jin Su Park ,  Ho Seok Em

IPC分类号： G11C13/00 ,  G11C5/06 ,  G11C5/14 ,  G05F3/02

摘要： A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

公开(公告)号：US10482971B2

公开(公告)日：2019-11-19

申请号：US16014306

申请日：2018-06-21

申请人： SK hynix Inc.

发明人： Jin Su Park ,  Taek Seung Kim

IPC分类号： G11C11/00 ,  G11C16/10 ,  G11C13/00 ,  G11C7/06 ,  G11C7/10

摘要： A semiconductor memory apparatus includes a memory cell. The semiconductor apparatus includes a current supply circuit configured to change a resistance state of the memory cell, by changing an amount of current flowing through the memory cell, with or without limiting a voltage level across the memory cell to a level of a clamping voltage based on a state of the memory cell.

公开(公告)号：US09899091B2

公开(公告)日：2018-02-20

申请号：US15629987

申请日：2017-06-22

申请人： SK hynix Inc.

发明人： Yeong Joon Son ,  Jin Su Park

IPC分类号： G11C16/06 ,  G11C16/12 ,  H03K17/687 ,  G11C16/04 ,  H03K17/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/30 ,  G11C5/14

CPC分类号： G11C16/12 ,  G11C5/145 ,  G11C5/147 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H03K17/102 ,  H03K17/6871

摘要： There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.

公开(公告)号：US09152326B2

公开(公告)日：2015-10-06

申请号：US13845433

申请日：2013-03-18

申请人： SK hynix Inc.

发明人： Wan Seob Lee ,  Jin Su Park

IPC分类号： G11C29/26 ,  G06F3/06 ,  G11C29/00

CPC分类号： G06F3/0619 ,  G11C29/785 ,  G11C29/846 ,  G11C2229/723

摘要： A semiconductor memory device includes a memory cell array configured to include sub memory blocks and a redundancy memory block, data line groups configured to deliver data to be programmed into the sub memory blocks and data read from the sub memory blocks, a redundancy data line group configured to deliver data to be programmed into the redundancy memory block and data read from the redundancy memory block, and switching circuits configured to couple selectively the data line groups to the redundancy data line group.

摘要翻译： 半导体存储器件包括被配置为包括子存储器块和冗余存储器块的存储单元阵列，被配置为将要编程的数据传送到子存储器块中的数据线组和从子存储块读取的数据，冗余数据线组 被配置为将要编程的数据传送到冗余存储器块中，以及从冗余存储器块读取的数据以及被配置为将数据线组选择性地耦合到冗余数据线组的开关电路。

公开(公告)号：US08824232B2

公开(公告)日：2014-09-02

申请号：US13846854

申请日：2013-03-18

申请人： SK hynix Inc.

发明人： Byoung Sung Yoo ,  Jin Su Park

IPC分类号： G11C7/12

CPC分类号： G11C7/12 ,  G11C7/1084 ,  G11C16/24 ,  G11C16/26

摘要： A semiconductor memory device may include a cell string configured to include memory cells, a page buffer coupled to the cell string through a bit line, and configured to include a latch for storing data to be programmed in a memory cell or data read from the memory cell, a precharge voltage generation circuit configured to generate a precharge voltage from an external voltage according to the data stored in the latch, bit line precharge circuits configured to supply the precharge voltage to the bit line in response to precharge control signals, and a control circuit configured to output the precharge control signals so that the number of enabled bit line precharge circuits increases, accordingly, as a supply number of a program voltage augments in a program operation.

摘要翻译： 半导体存储器件可以包括被配置为包括存储器单元的单元串，通过位线耦合到单元串的页缓冲器，并且被配置为包括用于存储要被编程在存储器单元中的数据或从存储器读取的数据的锁存器 单元，预充电电压产生电路，被配置为根据存储在所述锁存器中的数据从外部电压产生预充电电压，所述位线预充电电路被配置为响应于预充电控制信号将预充电电压提供给所述位线;以及控制 电路被配置为输出预充电控制信号，使得使能的位线预充电电路的数量增加，因此，在程序运行中增加编程电压的供给数量。

公开(公告)号：US11031077B2

公开(公告)日：2021-06-08

申请号：US16715343

申请日：2019-12-16

申请人： SK hynix Inc.

发明人： Ki Won Lee ,  Jin Su Park

IPC分类号： G11C13/00 ,  H01L27/24

摘要： A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.