公开(公告)号：US09620626B2

公开(公告)日：2017-04-11

申请号：US14272660

申请日：2014-05-08

Applicant: Soitec ,  STMicroelectronics, Inc.

Inventor： Frédéric Allibert ,  Pierre Morin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/02694 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/205

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

公开(公告)号：US20150325686A1

公开(公告)日：2015-11-12

申请号：US14272660

申请日：2014-05-08

Applicant: SOITEC ,  STMICROELECTRONICS, INC.

Inventor： Frédéric Allibert ,  Pierre Morin

IPC: H01L29/66 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02614 ,  H01L21/02694 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/205

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

Abstract translation: 制造半导体结构的方法涉及形成具有不同应力/应变状态的finFET晶体管的翅片。 可以使用一个应力/应变状态的芯来形成n型finFET，而可以采用另一个应力/应变状态的翅片来形成p型finFET。 具有不同应力/应变状态的翅片可以由公共半导体材料层制造。 使用这种方法制造半导体结构和器件。

公开(公告)号：US11974505B2

公开(公告)日：2024-04-30

申请号：US17044132

申请日：2019-03-13

Applicant: Soitec

Inventor： Frédéric Allibert ,  Christelle Veytizou

IPC: H03H9/02 ,  H03H3/10 ,  H10N30/00 ,  H10N30/079 ,  H10N30/097

CPC classification number: H10N30/10516 ,  H03H3/10 ,  H03H9/02559 ,  H03H9/02574 ,  H03H9/02834 ,  H10N30/079 ,  H10N30/097

Abstract: A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.

公开(公告)号：US20220359272A1

公开(公告)日：2022-11-10

申请号：US17623499

申请日：2020-03-25

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  Soitec

Inventor： Emmanuel Augendre ,  Frédéric Gaillard ,  Thomas Lorne ,  Emmanuel Rolland ,  Christelle Veytizou ,  Isabelle Bertrand ,  Frédéric Allibert

IPC: H01L21/762 ,  H01L21/02

Abstract: A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm.cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm.cm. The invention also relates to a method for producing such a semiconductor structure.

公开(公告)号：US20230207382A1

公开(公告)日：2023-06-29

申请号：US17998833

申请日：2021-05-18

Applicant: Soitec

Inventor： Isabelle Bertrand ,  Walter Schwarzenbach ,  Frédéric Allibert

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: A method for fabricating a semiconductor-on-insulator substrate for radiofrequency applications, comprises:



forming a donor substrate through epitaxial growth of an undoped semiconductor layer on a p-doped semiconductor seed substrate;
forming an electrically insulating layer on the undoped epitaxial semiconductor,
implanting ion species through the electrically insulating layer, so as to form, in the undoped epitaxial semiconductor layer, a weakened area defining a semiconductor thin layer to be transferred,
providing a semiconductor carrier substrate having an electrical resistivity greater than or equal to 500 Ω·cm,
bonding the donor substrate to the carrier substrate via the electrically insulating layer, and
detaching the donor substrate along the weakened area of embrittlement so as to transfer the semiconductor thin layer from the donor substrate to the carrier substrate.

公开(公告)号：US20230025429A1

公开(公告)日：2023-01-26

申请号：US17757822

申请日：2021-01-07

Applicant: Soitec

Inventor： Aymen Ghorbel ,  Frédéric Allibert ,  Damien Massy ,  Isabelle Bertrand ,  Lamia Nouri

IPC: H01L21/761 ,  H01L21/762

Abstract: The invention relates to a method for manufacturing a semiconductor-on-insulator structure (10), comprising the following steps: —providing an FD-SOI substrate (1) comprising, successively from its base to its top: a monocrystalline substrate (2) having an electrical resistivity of between 500 Ω·cm and 30 kΩ·cm, an interstitial oxygen content (Oi) of between 20 and 40 old ppma, and having an N- or P-type doping, an electrically insulating layer (3) having a thickness of between 20 nm and 400 nm, a monocrystalline layer (4) having a P-type doping, —heat-treating the FD-SOI substrate (1) at a temperature greater than or equal to 1175° C. for a time greater than or equal to 1 hour in order to form a P-N junction (5) in the substrate. The invention also relates to such a semiconductor-on-insulator structure.

公开(公告)号：US20220076992A1

公开(公告)日：2022-03-10

申请号：US17417715

申请日：2019-12-23

Applicant: Soitec

Inventor： Yvan Morandini ,  Walter Schwarzenbach ,  Frédéric Allibert ,  Eric Desbonnets ,  Bich-Yen Nguyen

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/322 ,  H01L27/12 ,  H01L29/06

Abstract: A semiconductor-on-insulator multilayer structure, comprises: —a stack, called the back stack, of the following layers from a back side to a front side of the structure: a semiconductor carrier substrate the electrical resistivity of which is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, a first semiconductor layer, —at least one trench isolation that extends through the back stack at least down to the first electrically insulating layer), and that electrically isolates two adjacent regions of the multilayer structure, the multilayer structure being characterized in that it further comprises at least one FD-SOI first region, and at least one RF-SOI second region.

公开(公告)号：US20210183691A1

公开(公告)日：2021-06-17

申请号：US17257176

申请日：2018-07-05

Applicant: Soitec

Inventor： Christelle Veytizou ,  Patrick Reynaud ,  Oleg Kononchuk ,  Frédéric Allibert

IPC: H01L21/762 ,  H01L21/02 ,  H01L23/66 ,  H01L29/16 ,  H01Q1/22

Abstract: A substrate for applications in the fields of radiofrequency electronics and microelectronics, comprises: a base substrate; a single carbon layer positioned on and directly in contact with the base substrate, with the carbon layer having a thickness ranging from 1 nm to 5 nm; an insulator layer positioned on the carbon layer; and a device layer positioned on the insulator layer. The disclosure also relates to a process for manufacturing such a substrate

公开(公告)号：US12119258B2

公开(公告)日：2024-10-15

申请号：US17623499

申请日：2020-03-25

Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  Soitec

Inventor： Emmanuel Augendre ,  Frédéric Gaillard ,  Thomas Lorne ,  Emmanuel Rolland ,  Christelle Veytizou ,  Isabelle Bertrand ,  Frédéric Allibert

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/762 ,  H01L23/64

CPC classification number: H01L21/76254 ,  H01L21/02164 ,  H01L21/02203 ,  H01L23/64

Abstract: A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm·cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm·cm. The invention also relates to a method for producing such a semiconductor structure.

公开(公告)号：US20230005787A1

公开(公告)日：2023-01-05

申请号：US17756244

申请日：2020-11-25

Applicant: Soitec

Inventor： Young-Pil Kim ,  Daniel Delprat ,  Luciana Capello ,  Isabelle Bertrand ,  Frédéric Allibert

IPC: H01L21/762 ,  H01L23/66 ,  H01L27/12 ,  H01L21/02

Abstract: A handle substrate for a composite structure comprises a base substrate including an epitaxial layer of silicon on a monocrystalline silicon wafer obtained by Czochralski pulling, a passivation layer on and in contact with the epitaxial layer of silicon, and a charge-trapping layer on and in contact with the passivation layer. The monocrystalline silicon wafer of the base substrate exhibits a resistivity of between 10 and 500 ohm·cm, while the epitaxial layer of silicon exhibits a resistivity of greater than 2000 ohm·cm and a thickness ranging from 2 to 100 microns. The passivation layer is amorphous or polycrystalline. A method is described for forming such a substrate.