公开(公告)号：US12170341B2

公开(公告)日：2024-12-17

申请号：US17579471

申请日：2022-01-19

Applicant: SRI International

Inventor： Winston K. Chan

IPC: H01L31/107 ,  G01J1/44 ,  G01S7/481 ,  G01S17/931 ,  H01L31/0304 ,  H01L31/0352 ,  H01L31/18

Abstract: A photodiode, such as a linear mode avalanche photodiode can be made free of excess noise via having a superlattice multiplication region that allows only one electrical current carrier type, such as an electron or a hole, to accumulate enough kinetic energy to impact ionize when biased, where the layers are lattice matched. A photodiode can be constructed with i) a lattice matched pair of a first semiconductor alloy and a second semiconductor alloy in a superlattice multiplication region, ii) an absorber region, and iii) a semiconductor substrate. A detector with multiple photodiodes can be made with these construction layers in order to have a cutoff wavelength varied anywhere from 1.7 to 4.9 μm as well as a noise resulting from a dark current at a level such that an electromagnetic radiation signal with the desired minimum wavelength cutoff can be accurately sensed by the photodiode.

公开(公告)号：US11735692B2

公开(公告)日：2023-08-22

申请号：US17297708

申请日：2019-08-22

Applicant: SRI International

Inventor： Winston K. Chan

IPC: H01L33/28 ,  H01L31/0296 ,  H01L31/109 ,  H01L31/18 ,  H01L33/00

CPC classification number: H01L33/28 ,  H01L31/02966 ,  H01L31/109 ,  H01L31/1832 ,  H01L33/002 ,  H01L33/0087

Abstract: Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.

公开(公告)号：US11569077B2

公开(公告)日：2023-01-31

申请号：US16629528

申请日：2018-07-11

Applicant: SRI International

Inventor： Sterling Eduardo McBride ,  Joey J. Michalchuk ,  Christopher E. Holland ,  Ashish Chaudhary ,  Winston K. Chan

IPC: H01J41/20 ,  F04B37/14 ,  H01J41/12 ,  H01J9/02 ,  H01J1/304 ,  H01J41/00 ,  H01J1/30 ,  H01J41/14 ,  H01J41/16 ,  H01J41/04 ,  H02K44/00 ,  B03C3/40 ,  G01L21/34 ,  F04B37/02 ,  B03C3/41

Abstract: The disclosure includes an outer electrode and an inner electrode. The outer electrode defines an inner volume and is configured to receive injected electrons through at least one aperture. The inner electrode positioned in the inner volume. The outer electrode and inner electrode are configured to confine the received electrons in orbits around the inner electrode in response to an electric potential between the outer electrode and the inner electrode. The apparatus does not include a component configured to generate an electron-confining magnetic field.

公开(公告)号：US20210217918A1

公开(公告)日：2021-07-15

申请号：US17056309

申请日：2018-07-11

Applicant: SRI International

Inventor： Winston K. Chan

IPC: H01L31/107 ,  G01J1/44 ,  H01L31/0352 ,  H01L31/0304

Abstract: A linear mode avalanche photodiode senses light and outputs electrical current by being configured to, generate a gain equal to or greater than 1000 times amplification while generating an excess noise factor of less than 3 times a thermal noise present at or above a non-cryogenic temperature due to the gain from the amplification. The linear mode avalanche photodiode detects one or more photons in the light by using a superlattice structure that is matched to suppress impact ionization for a first carrier in the linear mode avalanche photodiode while at least one of 1) increasing impact ionization, 2) substantially maintaining impact ionization, and 3) suppressing impact ionization to a lesser degree for a second carrier. The first carrier having its impact ionization suppressed is either i) an electron or ii) a hole; and then, the second carrier is the electron or the hole.

公开(公告)号：US20250120191A1

公开(公告)日：2025-04-10

申请号：US18836429

申请日：2022-12-21

Applicant: SRI International

Inventor： Winston K. Chan ,  David John Hill

IPC: H10F30/225 ,  G01S7/481 ,  H10F71/00 ,  H10F77/124 ,  H10F77/14

Abstract: An example Geiger mode avalanche photodiode includes a first semiconductor alloy forming a compositionally graded gain region configured to form a conduction band having free electrons, a valence band having free holes, and a bandgap between the valence band and the conduction band that varies in size across the graded gain region; a second semiconductor alloy forming an absorber region; and a semiconductor substrate.

公开(公告)号：US11688638B2

公开(公告)日：2023-06-27

申请号：US16497113

申请日：2018-03-27

Applicant: SRI International

Inventor： Winston K. Chan ,  Joey J. Michalchuk

IPC: H01L21/683 ,  H01L21/78 ,  B32B43/00 ,  C09J9/02 ,  C09J11/04 ,  C09J191/06 ,  H01L21/67 ,  H01L29/06 ,  C08K3/08

CPC classification number: H01L21/78 ,  B32B43/006 ,  C09J9/02 ,  C09J11/04 ,  C09J191/06 ,  H01L21/67092 ,  H01L21/6835 ,  H01L29/0657 ,  C08K2003/085 ,  C08K2003/0806 ,  C08K2003/0831 ,  C08K2201/001 ,  H01L2221/68327 ,  H01L2221/68381

Abstract: A system to manufacture a plurality of dies may include an etching tool, an electrically-conductive-adhesive-composition, a heat-applying-extraction-tool and a porous substrate cooperating with an evacuation component. The etching tool uses an ion beam that is configured to singulate a plurality of dies on a wafer with an ion etching process. The electrically-conductive-adhesive-composition is located between the wafer and a porous substrate carrying the wafer during the ion etching process. The electrically-conductive-adhesive-composition adheres the wafer to the porous substrate to keep the dies in place during the ion etching process. The electrically-conductive-adhesive-composition also aids in conducting electrons away from the wafer as a drain during the ion etching process. The heat-applying-extraction-tool applies heat to an individual die during a handling process of the manufacturing process in order to melt the electrically-conductive-adhesive-composition through the porous substrate to an evacuation component in order to then pick up an individual die singulated from the wafer.

公开(公告)号：US20220209040A1

公开(公告)日：2022-06-30

申请号：US17579471

申请日：2022-01-19

Applicant: SRI International

Inventor： Winston K. Chan

IPC: H01L31/107 ,  G01J1/44 ,  H01L31/0304 ,  H01L31/0352 ,  G01S17/931 ,  G01S7/481 ,  H01L31/18

Abstract: A photodiode, such as a linear mode avalanche photodiode can be made free of excess noise via having a superlattice multiplication region that allows only one electrical current carrier type, such as an electron or a hole, to accumulate enough kinetic energy to impact ionize when biased, where the layers are lattice matched. A photodiode can be constructed with i) a lattice matched pair of a first semiconductor alloy and a second semiconductor alloy in a superlattice multiplication region, ii) an absorber region, and iii) a semiconductor substrate. A detector with multiple photodiodes can be made with these construction layers in order to have a cutoff wavelength varied anywhere from 1.7 to 4.9 μm as well as a noise resulting from a dark current at a level such that an electromagnetic radiation signal with the desired minimum wavelength cutoff can be accurately sensed by the photodiode.

公开(公告)号：US20210359160A1

公开(公告)日：2021-11-18

申请号：US17297708

申请日：2019-08-22

Applicant: SRI International

Inventor： Winston K. Chan

IPC: H01L33/28 ,  H01L31/0296 ,  H01L33/00 ,  H01L31/109 ,  H01L31/18

Abstract: Methods, systems, and apparatuses are described for a CMOS compatible substrate having multiple stacks of semiconductor layers. The multiple stacks, at least, each include i) a layer of a tellurium based semiconductor layer on top of ii) a porous silicon layer. The porous silicon layer is a compliant layer to accept structural defects from the tellurium based semiconductor layer into the porous silicon layer. The multiple stacks are grown on the CMOS compatible substrate.

公开(公告)号：US20210158121A1

公开(公告)日：2021-05-27

申请号：US16497098

申请日：2018-03-27

Applicant: SRI International

Inventor： Sterling E. McBride ,  Michael G. Kane ,  Alex Krasner ,  Richard Sita ,  Winston K. Chan ,  Mark F. Schutzer

IPC: G06K19/07 ,  G06K19/073 ,  G06K19/077 ,  G06K9/00 ,  H04L9/32 ,  H04L9/08

Abstract: An integrated circuit having Radio Frequency Identification components and circuitry used for authentication is discussed. The RFID components and circuitry include two or more coils and corresponding electrical circuits that are tuned to use two or more different resonant frequencies including: a first resonant RF used for power generation and a second resonant RF used for data communication. The integrated circuit contains a unique signature that is used for the authentication with two or more aspects including i) a first aspect that is a programmed password in a memory embedded on the integrated circuit, and ii) a second aspect that is a unique, randomly generated code based upon a physical characteristic of the integrated circuit.

公开(公告)号：US20210125867A1

公开(公告)日：2021-04-29

申请号：US16497113

申请日：2018-03-27

Applicant: SRI International

Inventor： Winston K. Chan ,  Joey J. Michalchuk

IPC: H01L21/78 ,  H01L21/67 ,  H01L21/683 ,  H01L29/06 ,  C09J191/06 ,  C09J11/04 ,  C09J9/02 ,  B32B43/00

Abstract: A system to manufacture a plurality of dies may include an etching tool, an electrically-conductive-adhesive-composition, a heat-applying-extraction-tool and a porous substrate cooperating with an evacuation component. The etching tool uses an ion beam that is configured to singulate a plurality of dies on a wafer with an ion etching process. The electrically-conductive-adhesive-composition is located between the wafer and a porous substrate carrying the wafer during the ion etching process. The electrically-conductive-adhesive-composition adheres the wafer to the porous substrate to keep the dies in place during the ion etching process. The electrically-conductive-adhesive-composition also aids in conducting electrons away from the wafer as a drain during the ion etching process. The heat-applying-extraction-tool applies heat to an individual die during a handling process of the manufacturing process in order to melt the electrically-conductive-adhesive-composition through the porous substrate to an evacuation component in order to then pick up an individual die singulated from the wafer.