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1.发明申请METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT 有权处理交易方法，相关系统和计算机程序产品公开(公告)号：US20140289439A1
公开(公告)日：2014-09-25
申请号：US14219850
申请日：2014-03-19
IPC分类号： G06F13/40
CPC分类号： G06F13/4027 , G06F13/14 , G06F15/7825 , G06F2213/0038 , H04Q2213/13399 , H04Q2213/399
摘要： A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
摘要翻译： 诸如片上系统的系统包括通过IP块生成交易的接口组件或PLUG，诸如通过虚拟通道服务于一个或多个客户端的互连。 客户端或客户端通过客户端/虚拟通道映射映射到虚拟通道。 虚拟通道被提供为与IP块中的第二组虚拟通道协作的接口组件中的第一组虚拟通道。 提供了第一组虚拟通道和第二组虚拟通道的第一和第二客户端/虚拟通道映射。 第一个和第二个客户端/虚拟通道映射是单独可编程的，并且彼此相互解耦。
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公开(公告)号：US20130268990A1
公开(公告)日：2013-10-10
申请号：US13789445
申请日：2013-03-07
IPC分类号： H04L12/24
CPC分类号： H04L41/5038 , H04L41/0896 , H04L41/5025 , H04L43/0882 , H04L47/20 , H04L47/22 , H04L47/2416
摘要： A method includes providing at least one target bandwidth for bandwidth usage on an interconnect, the target bandwidth being for traffic associated with a traffic initiator. The method also includes measuring a served bandwidth and resetting the measuring of served bandwidth in response to an occurrence of an event.
摘要翻译： 一种方法包括为互连上的带宽使用提供至少一个目标带宽，所述目标带宽用于与业务发起者相关联的流量。 该方法还包括测量服务带宽并且响应于事件的发生重置服务带宽的测量。
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公开(公告)号：US11614949B2
公开(公告)日：2023-03-28
申请号：US16899327
申请日：2020-06-11
IPC分类号： G06F13/40 , G06F9/4401 , G06F9/30 , G06F9/345 , G06F9/445
摘要： An integrated circuit comprises a processing unit configured for booting up with a set of boot instructions, then for determining the size of the instructions of an application programme and potentially rebooting on its own initiative, while being reconfigured, in order for it to execute the instructions of the application program. Only one boot memory is needed as a consequence.
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公开(公告)号：US10102171B2
公开(公告)日：2018-10-16
申请号：US15608857
申请日：2017-05-30
摘要： A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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公开(公告)号：US20140112149A1
公开(公告)日：2014-04-24
申请号：US14059252
申请日：2013-10-21
IPC分类号： H04L12/835
CPC分类号： H04L47/30 , G06F15/7825 , H04L47/12 , H04L47/263 , Y02D50/10
摘要： An apparatus includes an output configured to output data to a communication path of an interconnect for routing to a target and a rate controller configured to control a rate of the output data. The rate controller is configured to control the rate in response to feedback information from the target.
摘要翻译： 一种装置包括被配置为将数据输出到用于路由到目标的互连的通信路径的输出和被配置为控制输出数据的速率的速率控制器。 速率控制器被配置为响应于来自目标的反馈信息来控制速率。
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公开(公告)号：US20130103865A1
公开(公告)日：2013-04-25
申请号：US13658667
申请日：2012-10-23
IPC分类号： G06F3/00
CPC分类号： G06F13/387 , Y02D10/14 , Y02D10/151
摘要： A method for transmitting data on a configurable bus of z physical links, including receiving input data on an input bus at at least one of a plurality of data rates, selecting a number of physical links n, amongst the z physical links, on which data is to be transmitted, selecting a clock frequency f at which the data is to be transmitted on the configurable bus, wherein the selections of n and f are based on information concerning the at least one of the plurality of data rates, the number of links used on the input bus.
摘要翻译： 一种用于在z物理链路的可配置总线上发送数据的方法，包括以多个数据速率中的至少一个在输入总线上接收输入数据，在所述z个物理链路中选择数量的物理链路n， 将要发送的数据的时钟频率f选择在可配置总线上传送的时钟频率f，其中n和f的选择是基于与多个数据速率中的至少一个数据速率有关的信息，链路数量 用于输入总线。
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公开(公告)号：US10255207B2
公开(公告)日：2019-04-09
申请号：US14536014
申请日：2014-11-07
摘要： A system is configured to capture a set of interrupts and output the interrupts serially onto an interconnect. The interrupts, which are routed to a destination, may first be packetized such that additional information is associated with the interrupt within the packet.
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公开(公告)号：US09389979B2
公开(公告)日：2016-07-12
申请号：US14038501
申请日：2013-09-26
CPC分类号： G06F11/27 , G06F11/2236 , G06F11/3648
摘要： A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.
摘要翻译： 系统包括处理器和通过互连网络连接的多个电路，其中与每个电路相关联的是相应的通信接口，被配置为在相应电路和互连网络之间交换数据。 特别地，调试单元与每个通信接口相关联。 每个调试单元可配置为数据插入点，其中调试单元通过相应的通信接口将数据发送到互连网络，或者每个调试单元可配置为数据接收点，其中调试单元通过 来自互连网络的相应通信接口的装置。
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公开(公告)号：US10019399B2
公开(公告)日：2018-07-10
申请号：US14940026
申请日：2015-11-12
IPC分类号： G06F17/50 , G06F13/36 , H04L12/933 , G06F15/78 , H04L12/935 , G06F13/40
CPC分类号： G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
摘要： A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
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公开(公告)号：US20170270070A1
公开(公告)日：2017-09-21
申请号：US15608857
申请日：2017-05-30
CPC分类号： G06F13/4027 , G06F13/14 , G06F15/7825 , G06F2213/0038 , H04Q2213/13399 , H04Q2213/399
摘要： A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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