公开(公告)号：US20170363507A1

公开(公告)日：2017-12-21

申请号：US15694156

申请日：2017-09-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Jean-Francois Carpentier ,  Patrick Le Maitre ,  Jean-Robert Manouvrier ,  Charles Baudot ,  Bertrand Borot

IPC: G01M11/02 ,  G02B6/12 ,  G02B6/28 ,  G02B6/34

CPC classification number: G01M11/02 ,  G01M11/33 ,  G01R31/2656 ,  G01R31/27 ,  G01R31/2884 ,  G01R31/303 ,  G01R31/311 ,  G01R31/31728 ,  G01R35/00 ,  G02B6/00 ,  G02B6/12004 ,  G02B6/2808 ,  G02B6/34

Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

公开(公告)号：US09791346B1

公开(公告)日：2017-10-17

申请号：US15133614

申请日：2016-04-20

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Francois Carpentier ,  Patrick Lemaitre ,  Jean-Robert Manouvrier ,  Charles Baudot ,  Bertrand Borot

IPC: G01B9/00 ,  G01M11/02 ,  G02B6/28 ,  G02B6/34 ,  G02B6/12

CPC classification number: G01M11/02 ,  G01R31/2656 ,  G01R31/27 ,  G01R31/2884 ,  G01R31/303 ,  G01R31/311 ,  G01R31/31728 ,  G01R35/00 ,  G02B6/00 ,  G02B6/12004 ,  G02B6/2808 ,  G02B6/34

Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

公开(公告)号：US10274395B2

公开(公告)日：2019-04-30

申请号：US15694156

申请日：2017-09-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Jean-Francois Carpentier ,  Patrick Le Maitre ,  Jean-Robert Manouvrier ,  Charles Baudot ,  Bertrand Borot

IPC: G01M11/02 ,  G02B6/28 ,  G02B6/34 ,  G02B6/12 ,  G01R31/265 ,  G01R31/27 ,  G01R31/28 ,  G01R31/303 ,  G01R31/311 ,  G01R31/317 ,  G01R35/00 ,  G02B6/00 ,  G01M11/00

Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

公开(公告)号：US09709739B1

公开(公告)日：2017-07-18

申请号：US15450150

申请日：2017-03-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Francois Carpentier ,  Patrick Le Maitre ,  Bertrand Borot

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/02 ,  G02B6/30

CPC classification number: G02B6/125 ,  G02B6/02042 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/4249 ,  G02B6/43 ,  G02B2006/12142 ,  G02B2006/12147

Abstract: A coupling module includes optical couplers that are coupled to waveguides. The optical couplers are configured to couple to cores of a multi-core optical fiber. The waveguides each include an external part extending from the module and an internal part extending into the module for connecting the external part to the associated optical coupler. The external part of some of the waveguides extends in a preferential direction, while the external part of others of the waveguides extends in a direction opposite to the preferential direction. The internal parts may include a curved portion configured for forming a turn-back.

公开(公告)号：US11251175B2

公开(公告)日：2022-02-15

申请号：US16562963

申请日：2019-09-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Ayres ,  Bertrand Borot

IPC: H01L27/32 ,  H01L27/02 ,  G06F30/39 ,  G06F30/394 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088

Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.

公开(公告)号：US10446535B2

公开(公告)日：2019-10-15

申请号：US15137201

申请日：2016-04-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Ayres ,  Bertrand Borot

IPC: H01L23/48 ,  H01L27/02 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088

Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.

公开(公告)号：US11573260B2

公开(公告)日：2023-02-07

申请号：US17543337

申请日：2021-12-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Ayres ,  Bertrand Borot

IPC: G01R31/28

Abstract: An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.

公开(公告)号：US20170179104A1

公开(公告)日：2017-06-22

申请号：US15137201

申请日：2016-04-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Ayres ,  Bertrand Borot

IPC: H01L27/02 ,  H01L23/532 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/088

Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.

公开(公告)号：US10075694B2

公开(公告)日：2018-09-11

申请号：US15681135

申请日：2017-08-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Ayres ,  Bertrand Borot

IPC: H01L23/522 ,  H04N13/00 ,  G11C5/04 ,  G11C29/44 ,  B42D25/42 ,  B42D25/305

CPC classification number: H04N13/178 ,  B42D25/305 ,  B42D25/42 ,  G11C5/04 ,  G11C29/44 ,  H01L23/544 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/5444 ,  H01L2223/54473

Abstract: A semiconductor chip includes a plurality of superposed semiconductor levels. The semiconductor levels include a plurality of elementary circuits coupled to a common input node. Sensing circuits are coupled to elementary elements of different levels. The outputs of the sensing circuits are used to generate a number, which serves as an identification number of the semiconductor chip.