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公开(公告)号：US4707805A
公开(公告)日：1987-11-17
申请号：US657487
申请日：1984-10-03
申请人： Sadayuki Narusawa , Norio Tomisawa
发明人： Sadayuki Narusawa , Norio Tomisawa
CPC分类号： G11B20/10527 , G11B20/1426 , G11B20/1809 , G11B7/013
摘要： There is provided a data processing circuit for processing symbol data read from a disc of a digital audio system such as a DAD player. Each of the symbol data read from the disc is first stored into a buffer register and then transferred therefrom to a symbol memory in accordance with internal pulse signals, and the number of the pulse signals generated during a period required to process one frame of symbol data is greater than that of symbol data contained in one frame of symbol data. An address data for addressing a desired area of the symbol memory is formed by adding a reference address data generated by counting the internal frame synchronization signals to a relative address data generated by adding together a specific pair of addressing data read out from an address memory, the address memory storing a plurality of groups of addressing data to be used in accordance with each mode of operation of this circuit. When the symbol data is written into the symbol memory, the reference address data is modified by adding an output of an up/down-counter to compensate for jitters of the symbol data, the up/down-counter counting frame synchronization signals discriminated from the data read from the disc in one of upward and downward directions and counting the internal frame synchronization signals in the other of upward and downward directions.
摘要翻译： 提供了一种用于处理从诸如DAD播放器的数字音频系统的盘读取的符号数据的数据处理电路。 从盘读取的每个符号数据首先被存储到缓冲寄存器中，然后根据内部脉冲信号传送到符号存储器，并且在处理一帧符号数据所需的周期期间产生的脉冲信号的数量 大于包含在一帧符号数据中的符号数据。 用于寻址符号存储器的期望区域的地址数据通过将通过对内部帧同步信号进行计数而产生的参考地址数据与通过将从地址存储器读出的特定寻址数据对相加而生成的相对地址数据相加来形成， 地址存储器存储根据该电路的各种操作模式使用的多组寻址数据。 当符号数据被写入符号存储器时，通过将上/下计数器的输出相加来补偿参考地址数据，以补偿符号数据的抖动，从与该符号数据区分开的向上/向下计数器计数帧同步信号 在向上和向下的一个方向从盘读取的数据，并且对上下方向的另一个内部帧同步信号进行计数。
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公开(公告)号：US4646303A
公开(公告)日：1987-02-24
申请号：US643951
申请日：1984-08-24
申请人： Sadayuki Narusawa , Norio Tomisawa
发明人： Sadayuki Narusawa , Norio Tomisawa
CPC分类号： H03M13/15 , G11B20/1813
摘要： In a digital system, there is provided a circuit for detecting and correcting errors in a group of data using Reed-Solomon codes. The group of data is first stored in a memory, and syndromes of the data are produced by a syndrome calculation circuit and fed to an internal data bus. A first data conversion circuit converts the syndromes on the internal data bus into logarithmic values and a multiplier-divider circuit executes multiplication or division of the data on the internal data bus by addition and subtraction operations of the logarithmic values. A second data conversion circuit converts antilogarithmically data from the multiplier-divider circuit, and an addition and subtraction circuit executes addition or subtraction of the data from the second data conversion circuit. An error detection circuit detects whether a single error exists in the group of data in accordance with the syndromes, and an error detection signal representing existence of error and an error location signal representing error location are produced. An address control circuit addresses the memory in accordance with the error detection signal and the error location signal so that the memory outputs an error data. A data correction circuit adds one of the syndromes representing amount of data error on the internal data bus to the error data outputted from the memory to produce its correct data. A double data error can be detected and corrected using Reed-Solomon codes in a similar manner.
摘要翻译： 在数字系统中，提供了一种用于使用里德 - 所罗门码检测和校正一组数据中的错误的电路。 数据组首先存储在存储器中，并且数据的综合数据由校正子计算电路产生并馈送到内部数据总线。 第一数据转换电路将内部数据总线上的校正子转换成对数值，并且乘法器分频器电路通过对数值的加法和减法运算来执行内部数据总线上的数据的乘法或除法。 第二数据转换电路从乘法器分频器电路转换反对数数据，加法和减法电路执行来自第二数据转换电路的数据的加法或减法。 误差检测电路根据校正子检测数据组中是否存在单一误差，产生表示误差存在的误差检测信号和表示误差位置的误差位置信号。 地址控制电路根据错误检测信号和错误位置信号寻址存储器，使得存储器输出错误数据。 数据校正电路将表示内部数据总线上的数据错误量的校正子之一添加到从存储器输出的错误数据，以产生正确的数据。 可以使用Reed-Solomon码以类似的方式检测和纠正双重数据错误。
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公开(公告)号：USRE32069E
公开(公告)日：1986-01-21
申请号：US76319
申请日：1979-09-17
申请人： Norio Tomisawa
发明人： Norio Tomisawa
摘要： A device for detecting a key switch operation capable of detecting an operating state of a plurality of key switches which are commonly connected with respect to each row line (block line) at one terminal thereof and commonly connected with respect to each column line at the other terminal thereof, thereby constituting a switch matrix. If a signal is provided on all column lines, the signal is transmitted to a block line through a key switch which is in operation and thereby a block including the key switch in operation is detected. A signal is then supplied from the detected block line to a column line only through the key switch in operation in the detected block. The position of the key switch in operation is known by detecting the columnn line on which the signal arrives. According to an embodiment of the invention, capacitance elements are provided both on the block lines and on the column lines for effecting delivery of the signal by charging and discharging of these capacitance elements. There is also disclosed a construction in which detected blocks are once stored in a memory and positions of key switches in operation in the detected blocks are detected and stored block by block. The stored blocks and key switch positions are codified to produce key codes identifying the key switches in operation.
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公开(公告)号：US5039893A
公开(公告)日：1991-08-13
申请号：US448056
申请日：1989-12-08
申请人： Norio Tomisawa
发明人： Norio Tomisawa
CPC分类号： H03K5/133 , G11B20/10009 , G11B20/225 , H03H11/265 , H03K3/0315 , H03K7/06 , H03K7/08 , H03K2005/00065 , H03K2005/00097 , H03K2005/00143 , H03K2005/00195
摘要： A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to a combination of an FM modulator and FM demodulator to provide a delay circuit for an analog circuit.
摘要翻译： 信号延迟装置包括CMOS门电路，其具有施加要延迟的二进制输入信号的输入端子，从其导出延迟信号的输出端子和施加操作电源电压的电源电压端子。 CMOS栅极电路的延迟时间取决于施加到其上的电压，并且利用该现象，电压控制装置设置在CMOS栅极电路的供电路径中，用于控制施加到CMOS栅极电路的电压。 使用CMOS门电路的信号延迟装置被应用于FM调制器和FM解调器的组合，以为模拟电路提供延迟电路。
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5.发明授权
公开(公告)号：US4641326A
公开(公告)日：1987-02-03
申请号：US659576
申请日：1984-10-10
申请人： Norio Tomisawa
发明人： Norio Tomisawa
CPC分类号： G11B27/3027 , G11B20/10 , G11B20/1208 , H04L7/041 , G11B20/1251 , G11B2020/10546 , G11B2020/1476 , G11B2220/2545
摘要： There is provided a counter circuit operable in synchronism with a frame of a digital data signal of a digital audio system even if a frame synchronization signal is not detected. The counter circuit comprises a detection circuit for detecting the frame synchronization signal of the digital data signal to produce a frame synchronization detection signal. A series of counters repeatedly count clock pulses reproduced from the digital data signal to produce a count signal when the count of the series of counters reaches a value corresponding to the number of channel bits includes in one (1) frame of the digital data signal. A reproduction frame sychronization signal is generated in response to the frame synchronization signal when the count of the series of counters is within a predetermined range, the reproduction frame synchronization signal resetting the counters. The reproduction frame synchronization signal is also generated in response to the count signal when the count of the series of counters is within the predetermined range and when the frame synchronization detection signal is not outputted from the frame synchronization signal detection circuit, the reproduction frame synchronization signal resetting the counters.
摘要翻译： 提供了即使没有检测到帧同步信号，也可以与数字音频系统的数字数据信号的帧同步地操作的计数器电路。 计数器电路包括检测电路，用于检测数字数据信号的帧同步信号以产生帧同步检测信号。 当一系列计数器的计数达到与数字数据信号的一（1）帧中的通道位数相对应的值时，一系列计数器重复对从数字数据信号再现的时钟脉冲进行计数，产生计数信号。 当一系列计数器的计数在预定范围内时，响应于帧同步信号产生再现帧同步信号，再现帧同步信号重置计数器。 当一系列计数器的计数在预定范围内时，还响应于计数信号产生再现帧同步信号，并且当帧同步检测信号不从帧同步信号检测电路输出时，再现帧同步信号 复位计数器。
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公开(公告)号：US4594703A
公开(公告)日：1986-06-10
申请号：US658263
申请日：1984-10-05
申请人： Norio Tomisawa , Shinji Aoshima
发明人： Norio Tomisawa , Shinji Aoshima
CPC分类号： G11B20/1403 , G11B20/1426 , G11B2020/1461
摘要： A simplified clock-signal reproducing circuit for reproducing a clock signal from a repetitive pulse signal or a digital signal such as an EFM signal read from a compact disc as a data recording medium of the compact disc digital audio system is provided. A voltage-controlled oscillator generates a first repetition signal, and a second repetition signal is formed from the first repetition signal, the second repetition signal being the clock signal. The repetitive pulse signal is latched by a first latch in response to the clock signal, and a signal which is a delayed output of the first latch is latched by a second latch in response to the clock signal. A voltage representing a phase difference between a clock signal in the repetitive pulse signal and the clock signal generated by the voltage-controlled oscillator is generated in accordance with a first phase difference between the input and output signals of the first latch and a second phase difference between input and output signals of the second latch. This voltage is applied to the voltage-controlled oscillator to thereby control the frequency of the first repetition signal so that the first and second phase differences become equal to each other and that the clock signal generated by the voltage-controlled oscillator and the clock signal existing in the repetitive pulse signal coincide in phase with each other.
摘要翻译： 提供了一种简化的时钟信号再现电路，用于从重复脉冲信号或数字信号（例如作为光盘数字音频系统的数据记录介质的光盘读取的EFM信号）再现时钟信号。 压控振荡器产生第一重复信号，并且第二重复信号由第一重复信号形成，第二重复信号是时钟信号。 响应于时钟信号，重复脉冲信号由第一锁存器锁存，响应于时钟信号，由第二锁存器锁存作为第一锁存器的延迟输出的信号。 根据第一锁存器的输入和输出信号与第二相位差之间的第一相位差产生表示重复脉冲信号中的时钟信号与由压控振荡器产生的时钟信号之间的相位差的电压 在第二锁存器的输入和输出信号之间。 该电压被施加到压控振荡器，从而控制第一重复信号的频率，使得第一和第二相位差变得彼此相等，并且由压控振荡器产生的时钟信号和存在的时钟信号 在重复脉冲信号中相互重合。
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公开(公告)号：US4339813A
公开(公告)日：1982-07-13
申请号：US183994
申请日：1980-09-04
CPC分类号： G11B3/08512
摘要： A groove-end detecting apparatus of a record disk or video disk, arranged to have a pulse generator for generating a pulse of a short period when the movement speed of the pickup arm is great, and having a long period when this movement speed is low, i.e. a pulse having a period inversely proportional to the movement speed of the pickup arm. This pulse is provided as a set pulse to a counter circuit assigned for counting a certain frequency clock pulse so as to generate a groove-end detection signal when the cycle is within the time which is required for the counting of a predetermined value of the count of the clock pulse.
摘要翻译： 一种记录盘或视盘的槽端检测装置，被配置为具有脉冲发生器，用于当拾取臂的移动速度大时产生短周期的脉冲，并且当该移动速度低时具有较长的周期 即具有与拾取臂的移动速度成反比的周期的脉冲。 该脉冲作为设定脉冲提供给被分配用于对特定频率时钟脉冲进行计数的计数器电路，以便当循环在计数预定值的计数所需的时间内时产生凹槽端检测信号 的时钟脉冲。
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公开(公告)号：US4109208A
公开(公告)日：1978-08-22
申请号：US556951
申请日：1975-03-10
CPC分类号： G10H7/04 , G10H1/0575
摘要： In a waveform producing system for use in, for example, an electronic musical instrument, a tone generator circuit and/or a tone control circuit including tone keyer circuits, each or either one of said tone generator circuit and said tone control circuit comprises: pulse generators associated with key-actuated switches, respectively; waveform memorizing means having at least one row of voltage dividers of which the division ratios are preset in characteristics corresponding to either the tone waveforms, the tone envelopes or the depression speeds of the key operated by the player of the instrument; sequential memory read-out means connected to the respective voltage dividers; and pulse generators thereby providing an enabling signal sequentially to the individual dividers every time a pulse is inputted from the pulse generators to read-out the memorized waveform in the form of a modified audio signal at the output side of the circuit. The memorized waveforms can arbitrarily be sampled (scanned) out by using a sampling circuit in the read-out means, thereby providing variations in the modified audio signal. The tone control circuit enables the tone level control in conformity to the depression speed of the key and tone envelope control without the need to employ the conventional charge-discharge circuit requiring a relatively large capacitance capacitor, and makes it easy to carry out circuit integration.
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9.发明授权Jitter control circuit having signal delay device using CMOS supply voltage control 失效具有使用CMOS电源电压控制的信号延迟器的抖动控制电路
公开(公告)号：US4956720A
公开(公告)日：1990-09-11
申请号：US448160
申请日：1989-12-08
申请人： Norio Tomisawa
发明人： Norio Tomisawa
CPC分类号： H03K5/133 , G11B20/10009 , G11B20/225 , H03H11/265 , H03K3/0315 , H03K7/06 , H03K7/08 , H03K2005/00065 , H03K2005/00097 , H03K2005/00143 , H03K2005/00195
摘要： A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.
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公开(公告)号：US4910448A
公开(公告)日：1990-03-20
申请号：US239132
申请日：1988-08-31
申请人： Norio Tomisawa , Mamoru Horino
发明人： Norio Tomisawa , Mamoru Horino
IPC分类号： G05B11/26 , G05B11/28 , G11B15/467 , H03K7/08 , H03K9/08
CPC分类号： G11B15/467 , G05B11/28
摘要： A PWM circuit for generating a PWM wave which is pulse-width modulated in response to binary information and is used for a signal such as a motor driving signal in an R-DAT (rotary head type digital audio tape recorder) comprises a circuit for dividing binary information such as a motor speed error signal provided for generating a PWM wave into plural bit groups and generates PWM waves corresponding to numerical values of these plural bit groups, and a circuit for weighting the generated PWM waves in an analog manner at a ratio corresponding to orders of the respective bit groups and adding the weighted PWM waves. Since binary information is divided into plural bit groups, the bit number of each bit group is small so that the period of PWM wave can be shortened without reducing the quantization bit number of the binary information or shortening reference clock period whereby accuracy of an error signal can be improved when the invention is applied to, e.g., a motor drive device.
摘要翻译： 一种PWM电路，用于产生响应于二进制信息进行脉冲宽度调制并用于诸如R-DAT（旋转磁头型数字音频磁带录像机）中的电动机驱动信号的信号的PWM波，包括用于分割的电路 二进制信息，例如用于将PWM波生成多个位组并产生对应于这些多个位组的数值的PWM波的电动机速度误差信号;以及用于以对应的比率以模拟方式对生成的PWM波进行加权的电路 到相应位组的顺序并加上加权的PWM波。 由于二进制信息被分成多个位组，所以每个位组的位数小，从而可以在不减少二进制信息的量化位数或缩短参考时钟周期的情况下缩短PWM波的周期，从而使误差信号的精度 当将本发明应用于例如电动机驱动装置时，可以得到改进。
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