利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.02 秒)

    Process for manufacturing a semiconductor material wafer having power regions dielectrically insulated from circuitry regions
    2.
    发明授权
    Process for manufacturing a semiconductor material wafer having power regions dielectrically insulated from circuitry regions 有权
    用于制造具有与电路区域介电绝缘的功率区域的半导体材料晶片的工艺

    公开(公告)号：US06331470B1

    公开(公告)日：2001-12-18

    申请号：US09580364

    申请日：2000-05-26

    申请人： Delfo Sanfilippo ,  Salvatore Leonardi

    发明人： Delfo Sanfilippo ,  Salvatore Leonardi

    IPC分类号： H01L21331

    CPC分类号： H01L21/76264 ,  H01L21/76281

    摘要： A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.

    摘要翻译： 从包括通过掩埋二氧化硅层彼此分离的顶部硅层和底部硅层的SOI型晶片开始进行制造工艺。 在顶层中，形成LOCOS型牺牲区，然后去除，以形成深度延伸到掩埋氧化物层的空腔。 随后，用外延或多晶硅填充空腔，以形成在晶片的顶表面和底表面之间延伸的功率区域; 然后形成将功率区域与电路区域绝缘的横向绝缘区域。

    Power semiconductor device structure with vertical PNP transistor
    4.
    发明授权
    Power semiconductor device structure with vertical PNP transistor 有权
    功率半导体器件结构采用垂直PNP晶体管

    公开(公告)号：US06518139B1

    公开(公告)日：2003-02-11

    申请号：US09569277

    申请日：2000-05-11

    申请人： Natale Aiello ,  Davide Patti ,  Salvatore Scaccianoce ,  Salvatore Leonardi

    发明人： Natale Aiello ,  Davide Patti ,  Salvatore Scaccianoce ,  Salvatore Leonardi

    IPC分类号： H01L218224

    CPC分类号： H01L27/0821 ,  H01L21/8224

    摘要： A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.

    摘要翻译： 形成在半导体材料芯片中的功率半导体器件结构包括N型衬底和N型外延层。 该结构包括形成其中形成控制电路的口袋的P型绝缘区域和多个完全绝缘的PNP功率晶体管。 每个PNP功率晶体管包括P型集电极区域，其包括在衬底和外延层之间的掩埋区域和接触区域。 P区域限定形成发射极P区域的基极N区域。

    Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device
    5.
    发明授权
    Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device 有权
    用于在惰性基板上集成至少包括无源元件和有源元件的器件以及相应的集成器件的工艺

    公开(公告)号：US08575720B2

    公开(公告)日：2013-11-05

    申请号：US11803716

    申请日：2007-05-14

    申请人： Salvatore Leonardi ,  Salvatore Coffa ,  Claudia Caligiore ,  Francesca Paola Tramontana

    发明人： Salvatore Leonardi ,  Salvatore Coffa ,  Claudia Caligiore ,  Francesca Paola Tramontana

    IPC分类号： H01L27/08

    CPC分类号： H01L21/84 ,  H01L27/12

    摘要： A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.

    摘要翻译： 描述了一种在惰性基板上集成具有至少一个无源部件和一个有源部件的装置的方法。 该方法包括：将保护电介质层沉积在惰性衬底上; 在保护电介质层上形成多晶硅岛; 有源元件在多晶硅岛上的集成; 覆盖电介质层沉积在保护电介质层和有源元件上; 将被动元件集成在覆盖介电层上; 在与所述有源部件的有源区域对应的覆盖介电层中实现的开口中形成第一接触结构; 以及与被动部件对应地形成第二接触结构。 还描述了通过该方法获得的集成装置。

    Thin-film transistor (TFT) device
    6.
    发明授权
    Thin-film transistor (TFT) device 有权
    薄膜晶体管（TFT）器件

    公开(公告)号：US07952104B2

    公开(公告)日：2011-05-31

    申请号：US12564719

    申请日：2009-09-22

    申请人： Salvatore Leonardi ,  Claudia Caligiore

    发明人： Salvatore Leonardi ,  Claudia Caligiore

    IPC分类号： H01L29/04 ,  H01L31/036

    CPC分类号： H01L21/02686 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1281 ,  H01L29/66757

    摘要： A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.

    摘要翻译： 一种薄膜晶体管器件的制造方法，其特征在于，在基板上形成介电绝缘层，在所述绝缘层上形成非晶硅层，使所述非晶硅层结晶化，得到多晶硅，在所述多晶硅上形成栅极结构 硅，并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。 所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域，然后使用激光照射所述非晶硅层，以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。

    RADIATION SENSOR WITH PHOTODIODES BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING INTEGRATION PROCESS
    7.
    发明申请
    RADIATION SENSOR WITH PHOTODIODES BEING INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING INTEGRATION PROCESS 审中-公开
    带有光电转换器的辐射传感器集成在半导体衬底和相应的集成工艺

    公开(公告)号：US20100163759A1

    公开(公告)日：2010-07-01

    申请号：US12649256

    申请日：2009-12-29

    申请人： Maria Eloisa Castagna ,  Salvatore Leonardi ,  Salvatore Abbisso ,  Lidia Maddiona

    发明人： Maria Eloisa Castagna ,  Salvatore Leonardi ,  Salvatore Abbisso ,  Lidia Maddiona

    IPC分类号： H01L31/14 ,  H01L31/0216 ,  H01L31/18

    CPC分类号： H01L31/18 ,  G01J1/0488 ,  G01J1/4204 ,  G01J1/4228 ,  H01L27/1443 ,  H01L31/02165

    摘要： An embodiment relates to a sensor integrated on a semiconductor substrate and comprising at least one first and second photodiode including at least one first and one second p-n junction made in such a semiconductor substrate as well as at least one first and one second antireflection coating made on top of such a first and second photodiode. At least one antireflection coating of such a first and second photodiode comprises at least one first and one second different antireflection layer to make a double layer antireflection coating suitable for obtaining for the corresponding photodiode a responsivity peak at a predetermined wavelength of an optical signal incident on the sensor. An embodiment also refers to an integration process of such a sensor, as well as to an ambient light sensor made with such a sensor.

    摘要翻译： 实施例涉及集成在半导体衬底上并包括至少一个第一和第二光电二极管的传感器，该至少一个第一和第二光电二极管包括在这种半导体衬底中形成的至少一个第一和一个第二pn结，以及至少一个第一和第二反射防止涂层 这样的第一和第二光电二极管的顶部。 这种第一和第二光电二极管的至少一个抗反射涂层包括至少一个第一和第二不同的抗反射层，以制造双层抗反射涂层，其适合于为相应的光电二极管获得在入射到其上的光信号的预定波长的响应峰 传感器。 实施例还涉及这种传感器以及由这种传感器制成的环境光传感器的集成过程。

    Process for manufacturing a thin-film transistor (TFT) device and TFT device manufactured by the process
    9.
    发明申请
    Process for manufacturing a thin-film transistor (TFT) device and TFT device manufactured by the process 有权
    用于制造薄膜晶体管（TFT）器件和通过该工艺制造的TFT器件的工艺

    公开(公告)号：US20070034872A1

    公开(公告)日：2007-02-15

    申请号：US11478332

    申请日：2006-06-28

    申请人： Salvatore Leonardi ,  Claudia Caligiore

    发明人： Salvatore Leonardi ,  Claudia Caligiore

    IPC分类号： H01L29/04

    CPC分类号： H01L21/02686 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1281 ,  H01L29/66757

    摘要： A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.

    摘要翻译： 一种薄膜晶体管器件的制造方法，其特征在于，在基板上形成介电绝缘层，在所述绝缘层上形成非晶硅层，使所述非晶硅层结晶化，得到多晶硅，在所述多晶硅上形成栅极结构 硅，并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。 所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域，然后使用激光照射所述非晶硅层，以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。