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    Integrated circuit including power gating circuit
    2.
    发明授权
    Integrated circuit including power gating circuit 有权

    公开(公告)号：US12249984B2

    公开(公告)日：2025-03-11

    申请号：US17886194

    申请日：2022-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

    IPC: H01L27/02 ,  G06F1/26 ,  H03K17/687 ,  H03K19/00 ,  H03K19/003

    Abstract: An integrated circuit includes a logic circuit comprising a plurality of logic transistors, the logic circuit comprising a plurality of logic gate lines extending in a first direction; and a power gating circuit comprising a plurality of power gating transistors, the power gating circuit comprising a first power gate line extending in a second direction that is perpendicular to the first direction, and the power gating circuit being connected to the logic circuit, wherein a plurality of source regions respectively included in the plurality of power gating transistors are connected to each other, or a plurality of drain regions respectively included in the plurality of power gating transistors are connected to each other.

    NONVOLATILE MEMORY DEVICE HAVING CELL ON PERIPHERY STRUCTURE
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING CELL ON PERIPHERY STRUCTURE 有权

    公开(公告)号：US20220115393A1

    公开(公告)日：2022-04-14

    申请号：US17345832

    申请日：2021-06-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Changyeon Yu ,  Pansuk Kwak

    IPC: H01L27/11573 ,  H01L21/66 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

    Abstract: A nonvolatile memory device having a cell over periphery (COP) structure includes a first sub memory plane and a second sub memory plane disposed adjacent to the first sub memory plane a row direction. A first vertical contact region is disposed in the cell region of the first sub memory plane and a second vertical contact region is disposed in the cell region of the second sub memory plane. A first overhead region is disposed in the cell region of the first sub memory plane and adjacent to the second vertical region in the row direction, and a second overhead region is disposed in the cell region of the second sub memory plane and adjacent the first vertical region in the row direction. Cell channel structures are disposed in a main region of the cell region.

    Vertical semiconductor device
    5.
    发明授权
    Vertical semiconductor device 有权

    公开(公告)号：US12278182B2

    公开(公告)日：2025-04-15

    申请号：US17721481

    申请日：2022-04-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

    IPC: H01L23/528 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

    Abstract: A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12002512B2

    公开(公告)日：2024-06-04

    申请号：US17709910

    申请日：2022-03-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changyeon Yu ,  Pansuk Kwak ,  Daeseok Byeon

    IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08

    CPC classification number: G11C16/0483 ,  G11C16/08

    Abstract: A semiconductor device includes a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including select transistors and memory cells; pass transistors configured to provide select signals to select lines connected to a selected memory block; and ground transistors configured to supply a first voltage to select lines connected to unselected memory blocks. The ground transistors include at least one common gate structure, at least one common active region, and individual active regions, and each of the common gate structure and the common active region are shared by two or more ground transistors, among the ground transistors. The common gate structure is between the common active region and the individual active regions, and includes a first region extending in a first direction and a second region extending in a second direction, intersecting the first direction.

    THREE-DIMENSIONAL MEMORY DEVICE
    8.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20240306394A1

    公开(公告)日：2024-09-12

    申请号：US18434356

    申请日：2024-02-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungun Lee ,  Pansuk Kwak ,  Changyeon Yu

    IPC: H10B43/40 ,  G11C16/08 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

    CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  G11C16/08

    Abstract: A memory device includes a stack structure, in which a common source line is formed, and a peripheral circuit structure overlapping the stack structure when viewed in plan view and comprising a common source line driver configured to discharge the common source line. The common source line driver includes a first common source line driving unit, electrically connected to the common source line through a first network and configured to discharge the common source line, and a second common source line driving unit electrically connected to the common source line through a second network, different from the first network, and configured to discharge the common source line. The first common source line driving unit and the second common source line driving unit are controlled independently of each other.

    Nonvolatile memory device and memory system including the same
    10.
    发明授权
    Nonvolatile memory device and memory system including the same 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号：US09251904B2

    公开(公告)日：2016-02-02

    申请号：US14458567

    申请日：2014-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doohyun Kim ,  Hyun Jun Yoon ,  Donghun Kwak ,  Kitae Park ,  Changyeon Yu

    IPC: G11C29/56 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/56

    Abstract: A nonvolatile memory device may include a memory cell array which is arranged in rows and columns and has multi-level memory cells; a voltage generator providing a plurality of read voltages to a selected row of the memory cell array; and control logic performing a plurality of page read operations using the read voltages. A first read voltage and a second read voltage among the plurality of read voltages are each associated with a higher probability of occurrence of a bit read error than at least one other read voltage among the plurality of read voltages. The control logic uses the first read voltage and the second read voltage in different page read operations than each other.

    Abstract translation: 非易失性存储器件可以包括以行和列布置并具有多级存储单元的存储单元阵列; 电压发生器，向存储单元阵列的选定行提供多个读取电压; 以及控制逻辑，使用读取的电压执行多个页面读取操作。 多个读取电压之间的第一读取电压和第二读取电压各自与多个读取电压中的至少一个其他读取电压的比特读取错误的发生概率相关。 控制逻辑在彼此不同的页读操作中使用第一读电压和第二读电压。

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