公开(公告)号：US3472443A

公开(公告)日：1969-10-14

申请号：US3472443D

申请日：1966-04-12

申请人： FANSTEEL INC

发明人： HOLZL ROBERT A ,  KOENIG WILLIAM D

IPC分类号： B23K20/00 ,  H01L21/00 ,  B23K1/00 ,  B23K3/00

CPC分类号： H01L24/85 ,  B23K20/005 ,  B23K2201/40 ,  H01L24/45 ,  H01L24/78 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4518 ,  H01L2224/45181 ,  H01L2224/45183 ,  H01L2224/45184 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/786 ,  H01L2224/85043 ,  H01L2224/851 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  Y10T29/49162 ,  Y10T29/49169 ,  Y10T29/49194 ,  H01L2224/48 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/2076 ,  H01L2924/20754

公开(公告)号：US3190954A

公开(公告)日：1965-06-22

申请号：US17145162

申请日：1962-02-06

申请人： CLEVITE CORP

发明人： POMERANTZ DANIEL I

IPC分类号： H01L21/607 ,  H01L23/488

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4518 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/4823 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/20751 ,  Y10S428/929 ,  Y10S428/938 ,  Y10T428/12528 ,  Y10T428/1275 ,  Y10T428/12778 ,  Y10T428/12826 ,  Y10T428/12889 ,  H01L2924/00014 ,  H01L2224/78 ,  H01L2924/00

摘要： 1,002,725. Semi-conductor devices. CLEVITE CORPORATION. Jan. 3, 1963 [Feb. 6, 1962], No. 361/63. Heading H1K. A semi-conductive element is provided with a lead wire formed of a core of relatively hard metal with an adherent coating of a relatively soft metal, attached to the element by thermocompression bonding. In the embodiment (Fig. 2) a semi-conductor element of silicon 22 is gold-alloyed to a header member (Fig. 1, not shown), and has a base region 24 formed in its surface by diffusion of boron into the element, and an emitter region 26 formed by diffusion of phosphorus. The diffusion areas may be defined by a SiO 2 mask pattern 29. Two aluminium strips 28 and 30 are provided on the element to which electrode connection is made by a molybdenum wire 10 having a gold coating 11 by a thermo-compression bonding technique. A portion of exposed molybdenum core 34 is subjected to a hydrogen peroxide etch to separate the electrode connections. The wire core may be nickel or tungsten with a silver coating.

公开(公告)号：US20240363655A1

公开(公告)日：2024-10-31

申请号：US18203700

申请日：2023-05-31

申请人： Reco BioTek Co., Ltd

发明人： Chang Cheng Fan ,  Chang Meng Chih ,  Tsai Cheng Feng

IPC分类号： H01L27/146 ,  H01L23/00 ,  H04N23/52

CPC分类号： H01L27/14618 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L27/1462 ,  H04N23/52 ,  H01L27/14645 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/4518 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73265

摘要： The present invention provides an image sensor module, including an integrated circuit substrate, an image sensing chip, a cover plate and an encapsulating material. The image sensing chip is disposed on the integrated circuit substrate. The image sensing chip includes an image sensing area and a non-image sensing area. A dam is disposed between the cover plate and the non-image sensing area of the image sensing chip. The cover plate includes a transparent material and a cushioning material. The encapsulating material covers the periphery of the image sensing chip, the periphery of the dam, part of the integrated circuit substrate and the periphery of the cover plate. The cushioning material is disposed between the transparent material and the dam and between the transparent material and the encapsulating material. The present invention reduces the possibility that the encapsulating material will peel off the cover plate.

公开(公告)号：US20120325517A1

公开(公告)日：2012-12-27

申请号：US13168675

申请日：2011-06-24

申请人： Cyprian Uzoh ,  Craig Mitchell

发明人： Cyprian Uzoh ,  Craig Mitchell

IPC分类号： H01B5/00 ,  H01B13/00

CPC分类号： H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45163 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45605 ,  H01L2224/45609 ,  H01L2224/45611 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/45693 ,  H01L2224/45887 ,  H01L2224/45893 ,  H01L2224/48 ,  H01L2224/85207 ,  H01L2924/01015 ,  H01L2924/10253 ,  Y10T29/49117 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01006

摘要： A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.

摘要翻译： 公开了一种可被配置用于半导体器件的导线结构。 线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。 包层可以是导体。 在各个方面，包覆层和芯具有不同的晶粒尺寸。 芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。 包覆层可以是在其厚度上具有不同浓度的次要组分的合金。 还公开了形成线结构的方法。

公开(公告)号：US09055700B2

公开(公告)日：2015-06-09

申请号：US13059602

申请日：2009-08-11

申请人： Mark Robson Humphries ,  Frank Ferdinandi ,  Rodney Edward Smith

发明人： Mark Robson Humphries ,  Frank Ferdinandi ,  Rodney Edward Smith

IPC分类号： H05K1/03 ,  H05K3/28 ,  H01L23/00 ,  H01H13/78 ,  H05K3/22 ,  H05K3/32

CPC分类号： H05K3/282 ,  H01H13/78 ,  H01H2215/004 ,  H01H2229/012 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/06 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45113 ,  H01L2224/45116 ,  H01L2224/4512 ,  H01L2224/45124 ,  H01L2224/45138 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45149 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/4517 ,  H01L2224/45171 ,  H01L2224/45173 ,  H01L2224/45178 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/45644 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/8502 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85484 ,  H01L2224/85611 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/3011 ,  H05K3/222 ,  H05K3/284 ,  H05K3/328 ,  H05K2201/015 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/049 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20758

摘要： In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multi-layer coating.

摘要翻译： 在一些实施例中，印刷电路板（PCB）包括包含绝缘材料的基板。 PCB还包括附接到基板的至少一个表面的多个导电轨迹。 PCB还包括沉积在衬底的至少一个表面上的多层涂层。 多层涂层（i）覆盖多个导电轨道的至少一部分，（ii）包括由卤代烃聚合物形成的至少一层。 PCB还包括至少一个通过焊接接头连接到至少一个导电轨道的电气部件，其中焊接接头通过多层涂层焊接，使得焊接接头邻接多层涂层。

公开(公告)号：US08692118B2

公开(公告)日：2014-04-08

申请号：US13168675

申请日：2011-06-24

申请人： Cyprian Uzoh ,  Craig Mitchell

发明人： Cyprian Uzoh ,  Craig Mitchell

IPC分类号： H01B5/00

CPC分类号： H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45163 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45605 ,  H01L2224/45609 ,  H01L2224/45611 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/45693 ,  H01L2224/45887 ,  H01L2224/45893 ,  H01L2224/48 ,  H01L2224/85207 ,  H01L2924/01015 ,  H01L2924/10253 ,  Y10T29/49117 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01006

摘要： A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.

摘要翻译： 公开了一种可被配置用于半导体器件的导线结构。 线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。 包层可以是导体。 在各个方面，包覆层和芯具有不同的晶粒尺寸。 芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。 包覆层可以是在其厚度上具有不同浓度的次要组分的合金。 还公开了形成线结构的方法。

公开(公告)号：US3742316A

公开(公告)日：1973-06-26

申请号：US3742316D

申请日：1972-01-28

申请人： NASA

发明人： FARRELL R

IPC分类号： H01L21/60 ,  H01L3/00 ,  H01L5/00

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/4518 ,  H01L2224/45647 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01322 ,  Y10S228/904 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/20752

摘要： A electronic device including lead attachment structure which permits operation of the devices over a wide temperature range. The device comprises a core conductor having a thin coating of metal thereon whereby only a limited amount of coating material is available to form an alloy which bonds the core conductor to the device electrode, the electrode composition thus being affected only in the region adjacent the lead and the bond between the electrode and device being unaffected.

公开(公告)号：US20140157592A1

公开(公告)日：2014-06-12

申请号：US14181466

申请日：2014-02-14

申请人： Tessera, Inc.

发明人： Cyprian Uzoh ,  Craig Mitchell

IPC分类号： H01B13/00

CPC分类号： H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/4516 ,  H01L2224/45163 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45573 ,  H01L2224/45605 ,  H01L2224/45609 ,  H01L2224/45611 ,  H01L2224/45644 ,  H01L2224/45647 ,  H01L2224/45655 ,  H01L2224/45657 ,  H01L2224/4568 ,  H01L2224/45686 ,  H01L2224/45693 ,  H01L2224/45887 ,  H01L2224/45893 ,  H01L2224/48 ,  H01L2224/85207 ,  H01L2924/01015 ,  H01L2924/10253 ,  Y10T29/49117 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/01006

摘要： A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have a different grain sizes. An average grain size of the core material may several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.

摘要翻译： 公开了一种可被配置用于半导体器件的导线结构。 线可以包括由导体材料形成的细长柔性芯和覆盖芯的外表面的覆层。 包层可以是导体。 在各个方面，包覆层和芯具有不同的晶粒尺寸。 芯材的平均晶粒尺寸可以比包覆层材料的平均晶粒尺寸大几个数量级。 包覆层可以是在其厚度上具有不同浓度的次要组分的合金。 还公开了形成线结构的方法。

公开(公告)号：US06693358B2

公开(公告)日：2004-02-17

申请号：US09972884

申请日：2001-10-10

申请人： Yuichiro Yamada ,  Tsuyoshi Hamatani

发明人： Yuichiro Yamada ,  Tsuyoshi Hamatani

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided. The semiconductor chip has a semiconductor substrate 13, first external electrodes 21 formed on the first surface 14 of the semiconductor substrate 13, second external electrodes 22 formed on the second surface 17 of the semiconductor substrate 13 and through holes 16 created in the semiconductor substrate 13, wherein the through holes 16 are provided in the inclined planes 15 formed so that the inner angles made up of the second surface 17 and the inclined planes 15 are obtuse angles and the first external electrodes 21 and the second external electrodes 22 are electrically connected through conductive patterns 19 formed so as to follow the inner walls of the through holes 16 and the inclined planes 15.

摘要翻译： 即使在多个半导体芯片层叠在布线基板上的情况下，半导体芯片也不会增加半导体器件的厚度或电路板面积，其中半导体芯片被层叠，并且不增加半导体芯片之间的线长度 其工艺以及半导体器件等。半导体芯片具有半导体衬底13，形成在半导体衬底13的第一表面14上的第一外部电极21，形成在半导体衬底13上的第二外部电极22 半导体基板13的第二表面17和在半导体基板13中形成的通孔16，其中通孔16设置在倾斜平面15中，使得由第二表面17和倾斜平面15构成的内角是 钝角和第一外部电极21和第二外部电极22通过导电性电连接 erns 19形成为跟随通孔16和倾斜平面15的内壁。

公开(公告)号：US20040017012A1

公开(公告)日：2004-01-29

申请号：US10616981

申请日：2003-07-11

发明人： Yuichiro Yamada ,  Tsuyoshi Hamatani

IPC分类号： H01L023/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided. The semiconductor chip has a semiconductor substrate 13, first external electrodes 21 formed on the first surface 14 of the semiconductor substrate 13, second external electrodes 22 formed on the second surface 17 of the semiconductor substrate 13 and through holes 16 created in the semiconductor substrate 13, wherein the through holes 16 are provided in the inclined planes 15 formed so that the inner angles made up of the second surface 17 and the inclined planes 15 are obtuse angles and the first external electrodes 21 and the second external electrodes 22 are electrically connected through conductive patterns 19 formed so as to follow the inner walls of the through holes 16 and the inclined planes 15.

摘要翻译： 即使在多个半导体芯片层叠在布线基板上的情况下，半导体芯片也不会增加半导体器件的厚度或电路板面积，其中半导体芯片被层叠，并且不增加半导体芯片之间的线长度 提供其工艺，以及半导体器件等。 半导体芯片具有半导体基板13，形成在半导体基板13的第一面14上的第一外部电极21，形成在半导体基板13的第二表面17上的第二外部电极22和在半导体基板13中形成的通孔16 其特征在于，所述通孔16设置在形成为由所述第二面17和所述倾斜面15构成的内角为钝角的倾斜面15中，所述第一外部电极21和所述第二外部电极22通过 导电图案19形成为跟随通孔16和倾斜平面15的内壁。