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公开(公告)号：US20180301178A1
公开(公告)日：2018-10-18
申请号：US15816810
申请日：2017-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： DAE-SHIK KIM , SUK-SOO PYO , GWAN-HYEOB KOH
CPC classification number: G11C11/1673 , G11C7/04 , G11C11/161 , G11C11/1697 , H01L27/228 , H01L43/08 , H01L43/10
Abstract: A memory device includes at least one reference cell and multiple memory cells. A method of operating the memory device may include detecting a temperature of the memory device and controlling a level of a first read signal applied to the at least one reference cell in accordance with a result of the detecting of the temperature. The method may also include comparing a first sensing value sensed by applying the first read signal to the at least one reference cell with a second sensing value sensed by applying a second read signal to a selected memory cell among the multiple memory cells.
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公开(公告)号：US20170278895A1
公开(公告)日：2017-09-28
申请号：US15387751
申请日：2016-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SONG-YI KIM , JAE-KYU LEE , DAE-HWAN KANG , GWAN-HYEOB KOH
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/144 , H01L45/1675
Abstract: A plurality of first conductive patterns is disposed on a substrate. Each of the plurality of first conductive patterns extends in a first direction. A first selection pattern is disposed on each of the plurality of first conductive patterns. A first barrier portion surrounds the first selection pattern. A first electrode and a first variable resistance pattern are disposed on the first selection pattern. A plurality of second conductive patterns is disposed on the first variable resistance pattern. Each of the plurality of second conductive patterns extends in a second direction crossing the first direction,
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公开(公告)号：US20210083171A1
公开(公告)日：2021-03-18
申请号：US17038779
申请日：2020-09-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： JUNG-HOON BAK , MYOUNG-SU SON , JAE-CHUL SHIM , GWAN-HYEOB KOH , YOON-JONG SONG
Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
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Patent Agency Ranking
公开(公告)号：US20200152869A1
公开(公告)日：2020-05-14
申请号：US16743594
申请日：2020-01-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JI-HYUN JEONG , JIN-WOO LEE , GWAN-HYEOB KOH , DAE-HWAN KANG
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US20170213870A1
公开(公告)日：2017-07-27
申请号：US15285922
申请日：2016-10-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KYU-RIE SIM , GWAN-HYEOB KOH , DAE-HWAN KANG
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1608 , H01L45/1675
Abstract: The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.
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公开(公告)号：US20190181342A1
公开(公告)日：2019-06-13
申请号：US16277685
申请日：2019-02-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KWANG-WOO LEE , DAE-HWAN KANG , GWAN-HYEOB KOH
Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.
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公开(公告)号：US20180145252A1
公开(公告)日：2018-05-24
申请号：US15862926
申请日：2018-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JI-HYUN JEONG , JIN-WOO LEE , GWAN-HYEOB KOH , DAE-HWAN KANG
CPC classification number: H01L45/144 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US20170271592A1
公开(公告)日：2017-09-21
申请号：US15366574
申请日：2016-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KWANG-WOO LEE , DAE-HWAN KANG , GWAN-HYEOB KOH
CPC classification number: H01L45/1675 , H01L27/2427 , H01L27/2481 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/144
Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.
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