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1.发明授权公开(公告)号：US11653113B2
公开(公告)日：2023-05-16
申请号：US17001053
申请日：2020-08-24
发明人： Moo Young Kim , Hyeok Jong Lee
CPC分类号： H04N5/3575 , H04N5/3765
摘要： An image sensor includes a pixel including a reset circuit and a floating diffusion node, and outputting a pixel signal that is generated based on a voltage at the floating diffusion node, the pixel signal including a reset output that is generated based on the voltage at the floating diffusion node being reset by the reset circuit. The image sensor further includes a sampler sampling the output pixel signal to generate a sampling signal having a time interval corresponding to a magnitude of the output pixel signal, and a counter counting the generated sampling signal, based on a counter clock, to generate a counting value corresponding to the time interval of the sampling signal. The sampler samples the reset output of the output pixel signal n times to generate first to n-th reset sampling signals, where n is an integer of 2 or more.
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公开(公告)号：US11445139B2
公开(公告)日：2022-09-13
申请号：US16746213
申请日：2020-01-17
发明人： Sung Yong Kim , Kyung-Min Kim , Hyuk Oh , Hyeok Jong Lee , Seung Hoon Jung , Woong Joo , Hee Sung Chae
摘要： An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.
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公开(公告)号：US09706156B2
公开(公告)日：2017-07-11
申请号：US14518085
申请日：2014-10-20
发明人： Hyeok Jong Lee , Jin Ho Seo , Young Tae Jang , Sung Ho Suh , Jin Young Jeong
CPC分类号： H04N5/76 , H04N3/1593 , H04N5/3415 , H04N5/343 , H04N5/3742
摘要： In one embodiment, an image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter configured to convert analog pixel signals output from the pixels into digital signals, a first cluster configured to store a first group of digital signals among the digital signals and to output first image data, a second cluster configured to store a second group of digital signals among the digital signals and to output second image data, and at least one cluster switch connected to the first cluster and the second cluster, a first channel, and a second channel. The image sensor is configured to transmit at least one among the first image data and the second image data to at least one among the first channel and the second channel based on an operation mode.
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公开(公告)号：US10397508B2
公开(公告)日：2019-08-27
申请号：US15435895
申请日：2017-02-17
发明人： Hyeok Jong Lee , Se-Jun Kim , Tomotasu Tate , Jin-Kyeong Heo
摘要： Disclosed are an image sensor having a light-emitting diode (LED) flicker mitigation function and an image processing system including the image sensor. The image processing system includes an image sensor including a plurality of pixels, the plurality of pixels configured to respectively generate pixel signals corresponding to photocharges, and configured to perform analog-to-digital conversion (ADC) on the pixel signals to generate digital pixel signals; and an image signal processor configured to process the digital pixel signals to generate image data. The image sensor operates in a first operating mode in a situation in which a light-emitting diode (LED) light is provided, and operates in a second operating mode in a general situation in which the LED light is not provided.
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公开(公告)号：US10038866B2
公开(公告)日：2018-07-31
申请号：US14854245
申请日：2015-09-15
发明人： Hyeok Jong Lee , Sung Ho Suh
CPC分类号： H04N5/378
摘要： An image sensor including a comparator configured to generate a comparison signal by comparing a ramp signal and a pixel signal with each other, a counter configured to generate a digital pixel value by counting an input clock signal according to the comparison signal, and a divider configured to control a frequency of the input clock signal according to an analog gain of the image sensor.
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公开(公告)号：US12096147B2
公开(公告)日：2024-09-17
申请号：US17878285
申请日：2022-08-01
发明人： Sung Yong Kim , Kyung-Min Kim , Hyuk Oh , Hyeok Jong Lee , Seung Hoon Jung , Woong Joo , Hee Sung Chae
IPC分类号： H04N25/75 , H04N25/709 , H03M1/56
CPC分类号： H04N25/75 , H04N25/709 , H03M1/56
摘要： An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.
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7.发明授权公开(公告)号：US10785429B2
公开(公告)日：2020-09-22
申请号：US16530583
申请日：2019-08-02
发明人： Moo Young Kim , Hyeok Jong Lee
摘要： An image sensor includes a pixel including a reset circuit and a floating diffusion node, and outputting a pixel signal that is generated based on a voltage at the floating diffusion node, the pixel signal including a reset output that is generated based on the voltage at the floating diffusion node being reset by the reset circuit. The image sensor further includes a sampler sampling the output pixel signal to generate a sampling signal having a time interval corresponding to a magnitude of the output pixel signal, and a counter counting the generated sampling signal, based on a counter clock, to generate a counting value corresponding to the time interval of the sampling signal. The sampler samples the reset output of the output pixel signal n times to generate first to n-th reset sampling signals, where n is an integer of 2 or more.
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公开(公告)号：US10194109B2
公开(公告)日：2019-01-29
申请号：US15295551
申请日：2016-10-17
发明人： Hyeok Jong Lee
IPC分类号： H04N5/376 , H04N5/378 , H01L27/146 , H04N5/3745
摘要： A data transfer circuit includes a first layer for transmitting first bits and a second layer for transmitting second bits. Each of the first layer and the second layer includes: first to mth banks configured to convert a plurality of received digital pixel signals into first to mth analog voltage signals, wherein ‘m’ denotes an integer which is greater than or equal to ‘2’; first to mth samplers configured to convert the first to mth analog voltage signals into first to mth digital transmission signals; and first to mth digital transfer units configured to respectively receive the first to mth digital transmission signals.
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公开(公告)号：US09860472B2
公开(公告)日：2018-01-02
申请号：US14990816
申请日：2016-01-08
发明人： Hyeok Jong Lee , Jin Ho Seo , Se Jun Kim , Sung Ho Suh , Young Tae Jang
IPC分类号： H04N5/217 , H04N5/378 , H04N5/347 , H04N5/365 , H04N5/374 , H04N5/3745 , H04N5/335 , H04N5/77
CPC分类号： H04N5/378 , H04N5/347 , H04N5/3658 , H04N5/374 , H04N5/3745 , H04N5/77
摘要： An image sensor operating in a skip mode and reading out a pixel signal provided by at least one of a plurality of pixels and compensating for fixed pattern noise (FPN) in column-parallel pipelines. The image sensor includes; a switch signal generator that generates a first switch control signal and a second switch control signal in response to FPN location information characterizing a first pipeline among the column-parallel pipelines as a noisy pipeline generating FPN, and characterizing a second pipeline among the column-parallel pipelines as a quiet pipeline not generating FPN, a binning switch block including a first switch controlled by the first switch control signal and a second switch controlled by the second switch control signal, wherein the first switch control signal causes the first pipeline to be inactivated and the second switch control signal causes the second pipeline to be activated, and a binning block that performs a digital binning operation on digital signals provided via the column-parallel pipelines including the second pipeline.
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公开(公告)号：US09060118B2
公开(公告)日：2015-06-16
申请号：US13827277
申请日：2013-03-14
发明人： Jin Hun Shin , Ji Min Cheon , Dong Hun Lee , Hyeok Jong Lee , Jin Ho Seo , Woo Seok Choi , Seog Heon Ham
CPC分类号： H04N5/23212 , H04N5/3696
摘要： Image sensors include an array of image sensor pixels therein. This array of image sensor pixels includes a first focus detection pixel and at least a first color pixel. A switching network is provided, which is electrically coupled to the array. This switching network may be configured to generate a first mixed image signal by electronically mixing a focus detection signal generated by the first focus detection pixel with at least one color pixel signal generated by the at least a first color pixel. The first focus detection pixel can be a color-blind pixel, which may include a light-blocking shield mask therein.
摘要翻译： 图像传感器包括其中的图像传感器像素阵列。 该图像传感器像素阵列包括第一焦点检测像素和至少第一颜色像素。 提供了一种与阵列电耦合的开关网络。 该切换网络可以被配置为通过将由第一焦点检测像素产生的焦点检测信号与由至少一个第一彩色像素生成的至少一个彩色像素信号电子混合来生成第一混合图像信号。 第一焦点检测像素可以是彩色盲像素，其可以在其中包括遮光屏蔽掩模。
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