公开(公告)号：US20170110197A1

公开(公告)日：2017-04-20

申请号：US15189136

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunkook PARK ,  Yeongtaek LEE ,  Daeseok BYEON

IPC: G11C16/28 ,  H03K5/24 ,  G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  H03K5/08 ,  G11C16/08

CPC classification number: G11C16/28 ,  G11C5/147 ,  G11C7/067 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C2013/0054 ,  H03K5/08 ,  H03K5/24

Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

公开(公告)号：US20240379162A1

公开(公告)日：2024-11-14

申请号：US18653627

申请日：2024-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyeon CHAE ,  Hyunkook PARK ,  Inmo KIM ,  Hanmin NAM

IPC: G11C16/08 ,  G11C5/06 ,  G11C16/04

Abstract: According to some embodiments of the inventive concept, there is provided a non-volatile memory device comprising: a memory cell array; a pass transistor circuit electrically connected to the memory cell array; a block select line group including a plurality of block select lines, wherein the plurality of block select lines comprises a first block select line and a second block select line, each of which extends in a first direction on a first layer, and the block select line group is electrically connected to the pass transistor circuit; and a first metal line extending in a second direction on a second layer, wherein the second layer is on the first layer, wherein at least one block select line includes at least one twist pattern that changes a path of the at least one block select line in a hole of the first metal line.

公开(公告)号：US20240233831A1

公开(公告)日：2024-07-11

申请号：US18512746

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungkyu CHO ,  Hyunkook PARK

IPC: G11C16/22 ,  G11C16/10

CPC classification number: G11C16/22 ,  G11C16/10 ,  G11C16/0483

Abstract: An operating method of a non-volatile memory device including a plurality of cell strings connected to a plurality of word lines, string select lines, and ground select lines includes applying a program voltage to a selected word line among the word lines during a program execution period, determining a discharge voltage by comparing the program voltage with a negative discharge reference voltage during the program execution period, applying a precharge voltage, which is less than the program voltage and greater than the discharge voltage, to the string select lines up to a first time point during a verify period following the program execution period, and applying the discharge voltage to a substrate of a string select transistor, which is connected to an unselected string select line among the string select lines, up to a second time point after the first time point during the verify period.

公开(公告)号：US20240062819A1

公开(公告)日：2024-02-22

申请号：US18131224

申请日：2023-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunkook PARK ,  Ahreum KIM ,  Pansuk KWAK

IPC: G11C16/08 ,  H01L23/48 ,  H10B80/00 ,  H01L23/528 ,  H01L25/065 ,  G11C16/04 ,  H01L23/00

CPC classification number: G11C16/08 ,  H01L23/481 ,  H10B80/00 ,  H01L23/5283 ,  H01L25/0657 ,  G11C16/0483 ,  H01L24/06 ,  H01L2224/05147 ,  H01L2224/065 ,  H01L2224/061 ,  H01L2224/0605 ,  H10B43/10

Abstract: A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.