公开(公告)号：US09311997B2

公开(公告)日：2016-04-12

申请号：US14069499

申请日：2013-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongkyu Lee ,  Sungyeon Lee ,  Yeongtaek Lee

IPC: G11C13/00 ,  G11C11/56 ,  G11C29/50 ,  G11C29/52 ,  G11C7/10 ,  G11C8/16 ,  G11C11/00 ,  G11C29/04

CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005 ,  G11C11/5607 ,  G11C11/5614 ,  G11C11/5642 ,  G11C11/5657 ,  G11C11/5678 ,  G11C29/50008 ,  G11C29/52 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2213/72

Abstract: A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first sink transistors is disposed between one end of the row line and a ground and the other of the first sink transistors is disposed between an opposite end of the row line and the ground. One of the second sink transistors is disposed between one end of the reference row line and the ground and the other of the second sink transistors is disposed between an opposite end of the reference row line and the ground. The word line is coupled to gates of the first and second sink transistors.

Abstract translation: 电阻式存储器件包括存储单元阵列块，参考单元阵列块，两个第一和第二宿晶体管以及字线。 每个存储单元阵列块包括行线，并且参考单元阵列块包括参考行线。 第一个晶体管中的一个设置在行线的一端和地之间，而另一个第一宿晶体管设置在行线的相对端和地之间。 第二宿晶体管中的一个设置在参考行线的一端和地之间，另一个第二宿晶体管设置在参考行线的相对端和地之间。 字线耦合到第一和第二宿晶体管的栅极。

公开(公告)号：US09552879B2

公开(公告)日：2017-01-24

申请号：US14505523

申请日：2014-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongkyu Lee ,  Yeongtaek Lee ,  Youngbae Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0097 ,  G11C11/5614 ,  G11C11/5685 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

Abstract: A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a corresponding compliance current, and then programming the memory cell to a reset state by pre-reading the variable resistance memory cell to determine its resistance and resetting the memory cell using a variable reset voltage determined in response to the determined resistance.

Abstract translation: 一种在非易失性存储器件中复位可变电阻存储单元的方法包括： 使用相应的顺应性电流将存储器单元编程为设定状态，然后通过预读可变电阻存储单元来确定其电阻并使用响应中确定的可变复位电压来复位存储单元来将存储单元编程为复位状态 到确定的阻力。

公开(公告)号：US09685237B2

公开(公告)日：2017-06-20

申请号：US15189136

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunkook Park ,  Yeongtaek Lee ,  Daeseok Byeon

IPC: G11C7/12 ,  G11C8/08 ,  G11C5/06 ,  G11C16/28 ,  H03K5/08 ,  H03K5/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C13/00 ,  G11C7/06 ,  G11C5/14

CPC classification number: G11C16/28 ,  G11C5/147 ,  G11C7/067 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C2013/0054 ,  H03K5/08 ,  H03K5/24

Abstract: Disclosed is a driver circuit. The driver circuit includes a clamp transistor, a comparison voltage transistor, an amplification transistor, a bias transistor, and a charge circuit. The comparison voltage is configured to provide a comparison voltage. The amplification transistor includes an amplification gate connected to a first node of the clamp transistor, a first amplification node configured to receive the comparison voltage, and a second amplification node connected to a gate of the clamp transistor. The bias transistor is configured to supply a bias voltage. The charge circuit is at least one of configured to drain a current from the first node through the clamp transistor and configured to supply a current to the first node through the clamp transistor.

公开(公告)号：US20140204652A1

公开(公告)日：2014-07-24

申请号：US14069499

申请日：2013-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkyu Lee ,  Sungyeon Lee ,  Yeongtaek Lee

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005 ,  G11C11/5607 ,  G11C11/5614 ,  G11C11/5642 ,  G11C11/5657 ,  G11C11/5678 ,  G11C29/50008 ,  G11C29/52 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2213/72

Abstract: A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line. One of the first sink transistors is disposed between one end of the row line and a ground and the other of the first sink transistors is disposed between an opposite end of the row line and the ground. One of the second sink transistors is disposed between one end of the reference row line and the ground and the other of the second sink transistors is disposed between an opposite end of the reference row line and the ground. The word line is coupled to gates of the first and second sink transistors.

Abstract translation: 电阻式存储器件包括存储单元阵列块，参考单元阵列块，两个第一和第二宿晶体管以及字线。 每个存储单元阵列块包括行线，并且参考单元阵列块包括参考行线。 第一个晶体管中的一个设置在行线的一端和地之间，而另一个第一宿晶体管设置在行线的相对端和地之间。 第二宿晶体管中的一个设置在参考行线的一端和地之间，另一个第二宿晶体管设置在参考行线的相对端和地之间。 字线耦合到第一和第二宿晶体管的栅极。

公开(公告)号：US20140192588A1

公开(公告)日：2014-07-10

申请号：US14146748

申请日：2014-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungyeon Lee ,  Yeongtaek Lee ,  Kiwon Lim ,  Wonryul Chung

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile memory device is provided which includes a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using the same write condition as that of the main area; a reference sense amplifier circuit configured to read data written at the reference area through the reference bit lines at a read operation; and control logic configured to control the reference sense amplifier circuit such that data written at the reference area is shifted with a weight scheme and then read, the data written at the reference area being used as a read reference value of the main area at a read operation.

Abstract translation: 提供了一种非易失性存储器件，包括：主区域，包括连接到字线和主位线的主单元; 参考区域，包括连接到字线和参考位线的参考单元，并使用与主区域相同的写入条件进行编程; 参考读出放大器电路，被配置为在读取操作时通过参考位线读取写入参考区域的数据; 以及控制逻辑，被配置为控制参考读出放大器电路，使得写入参考区域的数据以加权方案移位，然后读取，写入参考区域的数据被用作读取时的主区域的读取参考值 操作。