公开(公告)号：US09575112B2

公开(公告)日：2017-02-21

申请号：US14673490

申请日：2015-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Wook Oh ,  Chin Kim ,  Sunhom Steve Paak ,  Jae-Seok Yang

IPC: G01R31/36 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/319

CPC classification number: G01R31/2607 ,  G01R31/2601 ,  G01R31/31722 ,  G01R31/318511 ,  G01R31/31926

Abstract: A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.

Abstract translation: 测试系统包括行解码器，列解码器，行测试控制器和测试电路。 行解码器基于多个行输入信号来激活第一至第M行信号中的一个。 列解码器基于多个列输入信号来激活第一至第N列信号中的一个。 当行测试使能信号被激活时，行测试控制器首先输出第N列输出信号，这些信号被激活。 当行测试使能信号被去激活时，行测试控制器分别输出第一至第N列信号作为第一至第N列输出信号。 测试电路包括第一至第M行测试块，每个测试块包括第一至第N个测试单元。 当行测试使能信号被激活时，测试电路同时执行包括在行测试块中的第一至第N测试单元的短测试。

公开(公告)号：US20180012794A1

公开(公告)日：2018-01-11

申请号：US15703001

申请日：2017-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Wook Oh ,  Jong-Hyun Lee ,  Sung-Wook Hwang

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/66

CPC classification number: H01L21/76811 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76813 ,  H01L21/76816 ,  H01L22/20 ,  H01L23/522 ,  H01L23/528

Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

公开(公告)号：US11996402B2

公开(公告)日：2024-05-28

申请号：US17329669

申请日：2021-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Wook Oh ,  Byungyun Kang ,  Donghyun Kim ,  Hyungjune Kim ,  Jaebong Jung

IPC: H01L27/02 ,  H01L21/8238 ,  H01L23/48 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0207 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/481 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Disclosed is a semiconductor device comprising a substrate that includes a cell region and a dummy region, a first metal layer on the substrate and including a dummy line on the dummy region, a power delivery network on a bottom surface of the substrate, and a first through via that penetrates the substrate and extends from the power delivery network toward the dummy line. The first through via is electrically connected to the dummy line. The power delivery network includes a plurality of lower lines and a pad line below the lower lines. The pad line is electrically connected through the lower lines to the first through via.

公开(公告)号：US09824916B2

公开(公告)日：2017-11-21

申请号：US15250199

申请日：2016-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Wook Oh ,  Jong-Hyun Lee ,  Sung-Wook Hwang

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/033

CPC classification number: H01L21/76811 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76813 ,  H01L21/76816 ,  H01L22/20 ,  H01L23/522 ,  H01L23/528

Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

公开(公告)号：US10079172B2

公开(公告)日：2018-09-18

申请号：US15703001

申请日：2017-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Wook Oh ,  Jong-Hyun Lee ,  Sung-Wook Hwang

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/033 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76811 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76813 ,  H01L21/76816 ,  H01L22/20 ,  H01L23/522 ,  H01L23/528

Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

公开(公告)号：US09871122B2

公开(公告)日：2018-01-16

申请号：US15244265

申请日：2016-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Wook Oh ,  Hyunjae Lee ,  Jaeseok Yang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/32 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L29/6681 ,  H01L21/76816 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/3223

Abstract: A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy active patterns on the dummy region. The first and second main regions are spaced apart from each other in a first direction and the dummy region includes a dummy connection region between the first and second main regions and first and second dummy cell regions spaced apart from each other in a second direction. First dummy active patterns, second dummy active patterns, and connection dummy active patterns connecting some of the first dummy active patterns to some of the second dummy active patterns are provided on the first and second dummy cell regions and the dummy connection region, respectively.