公开(公告)号：US20210183663A1

公开(公告)日：2021-06-17

申请号：US17188404

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho LEE ,  Hyunsoo CHUNG ,  Hansung RYU ,  InYoung LEE

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20200273723A1

公开(公告)日：2020-08-27

申请号：US15930935

申请日：2020-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho LEE ,  Hyunsoo CHUNG ,  Hansung RYU ,  InYoung LEE

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L23/58 ,  H01L23/373 ,  H01L21/48 ,  H01L21/02 ,  H01L23/544 ,  H01L25/065 ,  H01L21/768

Abstract: A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20180315620A1

公开(公告)日：2018-11-01

申请号：US15815032

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho LEE ,  Hyunsoo CHUNG ,  Hansung RYU ,  InYoung LEE

IPC: H01L21/50 ,  H01L23/48 ,  H01L23/00 ,  H01L21/02 ,  H01L23/373 ,  H01L21/48 ,  H01L23/58

CPC classification number: H01L21/50 ,  H01L21/02118 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/481 ,  H01L23/544 ,  H01L23/58 ,  H01L24/02 ,  H01L25/0657 ,  H01L2223/54426

Abstract: A semiconductor device including a substrate, an insulating, layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

公开(公告)号：US20150318261A1

公开(公告)日：2015-11-05

申请号：US14611585

申请日：2015-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo CHUNG ,  InYoung LEE ,  Taeje CHO

IPC: H01L25/065 ,  H01L21/306 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/29 ,  H01L21/768 ,  H01L21/304

CPC classification number: H01L25/50 ,  H01L21/3043 ,  H01L21/30604 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/00 ,  H01L23/29 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/03 ,  H01L24/08 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/92125 ,  H01L2224/92152 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83

Abstract: The method of fabricating a semiconductor package including preparing a semiconductor wafer having a first side and a second side, the second side facing the first side, and the semiconductor wafer including a through via exposed through the first side, forming trenches at cutting areas between chip areas and at edge areas of the semiconductor wafer on the first side, stacking a semiconductor chip on the through via, forming an under fill resin layer to fill a gap between the semiconductor chip and the semiconductor wafer and to cover a side of the semiconductor chip, and forming a molding layer to cover at least a portion of the under fill resin layer and to fill at least a portion of the respective trenches may be provided.

Abstract translation: 一种制造半导体封装的方法，包括制备具有第一侧和第二侧的半导体晶片，面向第一侧的第二面，以及包括通过第一侧露出的通孔的半导体晶片，在芯片之间的切割区域处形成沟槽 区域和第一侧的半导体晶片的边缘区域，在通孔上堆叠半导体芯片，形成下填充树脂层以填充半导体芯片和半导体晶片之间的间隙并覆盖半导体芯片的一侧 并且可以提供形成模制层以覆盖下填充树脂层的至少一部分并填充相应沟槽的至少一部分。