公开(公告)号：US09087602B2

公开(公告)日：2015-07-21

申请号：US14219374

申请日：2014-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youn Youn ,  Su-A Kim ,  Chul-Woo Park ,  Young-Soo Sohn

IPC: G11C7/20 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C7/1063 ,  G11C11/40611 ,  G11C11/40618

Abstract: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.

Abstract translation: 提供了一种易失性存储器件的刷新方法。 该方法包括：随着对第一存储器区域的访问次数的增加，检测影响第二存储器区域的多个干扰; 当检测到的干扰次数达到参考值时，将来自易失性存储器件的警报信号输出到易失性存储器件的外部; 以及响应于所述警报信号对所述第二存储区域执行刷新操作。

公开(公告)号：US09064603B1

公开(公告)日：2015-06-23

申请号：US14185302

申请日：2014-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Youn Youn ,  Su-A Kim ,  Hyo-Jin Choi ,  Chul-Woo Park ,  Hak-Soo Yu

IPC: G11C7/10 ,  G11C11/409

CPC classification number: G11C11/40626 ,  G06F11/106 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/22 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409

Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.

Abstract translation: 半导体存储器件包括存储单元阵列和控制逻辑。 存储单元阵列包括第一和第二子阵列，第一子阵列包括第一组阵列阵列，而第二子阵列包括第二组阵列阵列。 上部和下部排列阵列中的每一个包括相对于彼此具有不同定时参数的第一和第二部分。 控制逻辑控制对第一和第二部分的访问，使得在第一和第二部分上执行读/写操作。

公开(公告)号：US10262935B2

公开(公告)日：2019-04-16

申请号：US15677054

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Ju Kim ,  Su-A Kim ,  Soo-Young Kim ,  Min-Woo Won ,  Bok-Yeon Won ,  Ji-Suk Kwon ,  Young-Ho Kim ,  Ji-Hak Yu ,  Hyun-Chul Yoon ,  Seok-Jae Lee ,  Sang-Keun Han ,  Woong-Dai Kang ,  Hyuk-Joon Kwon ,  Bum-Jae Lee

IPC: H01L23/522 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097 ,  H01L23/528 ,  H01L23/00 ,  H01L23/50 ,  H01L23/552 ,  G11C7/10 ,  G11C7/06

Abstract: A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

公开(公告)号：US09390778B2

公开(公告)日：2016-07-12

申请号：US14798164

申请日：2015-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-A Kim ,  Dae-Sun Kim ,  Dae-Jeong Kim ,  Sung-Min Ryu ,  Kwang-Il Park ,  Chul-Woo Park ,  Young-Soo Sohn ,  Jae-Youn Youn

IPC: G11C8/12 ,  G11C8/08 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4097

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract translation: 半导体存储器件包括存储单元阵列，子字线驱动器和功率选择开关。 存储单元阵列包括耦合到字线的存储单元行。 子字线驱动器耦合到字线。 功率选择开关耦合到子字线驱动器。 每个电源选择开关控制从字线激活的第一字线的去激活电压电平和与第一字线相邻的第二字线的截止电压电平，使得去激活电压电平和截止电压电平 具有接地电压，第一负电压和第二负电压中的至少一个。 接地电压，第一负电压和第二负电压彼此具有不同的电压电平。

公开(公告)号：US09653141B2

公开(公告)日：2017-05-16

申请号：US14858140

申请日：2015-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yun Kim ,  Jong-Pil Son ,  Su-A Kim ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC: G06F12/00 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/408 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

公开(公告)号：US09318168B2

公开(公告)日：2016-04-19

申请号：US14090510

申请日：2013-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Woo Park ,  Dong-Soo Kang ,  Su-A Kim ,  Jun-hee Yoo ,  Hak-Soo Yu ,  Jae-Youn Youn ,  Sung-hyun Lee ,  Kyoung-Heon Jeong ,  Hyo-Jin Choi ,  Young-Soo Sohn

IPC: G06F12/02 ,  G11C7/10 ,  G11C29/00

CPC classification number: G11C7/1072 ,  G06F12/0223 ,  G06F12/0292 ,  G11C29/76 ,  G11C29/84

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract translation: 在一个示例性实施例中，存储器系统包括存储器模块和存储器控制器。 配置存储器模块基于存储器模块的不良页面的数量生成存储器模块的密度信息，坏页面是具有故障的页面。 存储器控制器被配置为基于从存储器模块接收的密度信息将连续的物理地址映射到存储器模块的动态随机存取存储器（显存）地址。