公开(公告)号：US20180006219A1

公开(公告)日：2018-01-04

申请号：US15414911

申请日：2017-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hun SEO ,  Jung-Ik OH ,  Yoo-Chul KONG ,  Woo-Ram KIM ,  Jong-Chul PARK ,  Gwang-Hyun BAEK ,  Bok-Yeon WON ,  Hye-Jin CHOI

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L45/1675 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.

公开(公告)号：US20160372347A1

公开(公告)日：2016-12-22

申请号：US15008788

申请日：2016-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuk KIM ,  Ha-Na KIM ,  Kyoungsub SHIN ,  Jung-Ik OH

IPC: H01L21/67

CPC classification number: H01L21/67253 ,  F16K1/44 ,  F16K51/02 ,  H01L21/67017 ,  H01L21/67126

Abstract: Provided are a substrate processing apparatus capable of performing a semiconductor process using a plasma and a method of forming a semiconductor device using the same. The substrate processing apparatus includes a process chamber, a high vacuum pump, an exhaust flow path between the high vacuum pump and the process chamber, and a vacuum valve in the exhaust flow path. The vacuum valve includes a first valve and a second valve having a smaller orifice than the first valve.

Abstract translation: 提供了能够使用等离子体进行半导体处理的基板处理装置以及使用其形成半导体装置的方法。 基板处理装置包括处理室，高真空泵，高真空泵和处理室之间的排气流路以及排气流路中的真空阀。 真空阀包括具有比第一阀小的孔的第一阀和第二阀。

公开(公告)号：US20190139755A1

公开(公告)日：2019-05-09

申请号：US16240216

申请日：2019-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ik OH ,  Daehyun JANG ,  Ha-Na KIM ,  Kyoungsub SHIN

IPC: H01L21/027 ,  H01L27/24 ,  H01L27/11556 ,  H01L21/308 ,  H01L21/306 ,  H01L27/11582 ,  H01L27/11575

CPC classification number: H01L21/0274 ,  H01L21/30604 ,  H01L21/3085 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481 ,  H01L45/122 ,  H01L45/1253 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.