公开(公告)号：US20170345507A1

公开(公告)日：2017-11-30

申请号：US15680104

申请日：2017-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Chul PARK ,  Seung-Bum KIM ,  Myung-Hoon CHOI

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/34 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3477

Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

公开(公告)号：US20200052204A1

公开(公告)日：2020-02-13

申请号：US16658548

申请日：2019-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Chul PARK

IPC: H01L45/00 ,  H01L43/08 ,  H01L27/24

Abstract: A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.

公开(公告)号：US20180159030A1

公开(公告)日：2018-06-07

申请号：US15630087

申请日：2017-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Chul PARK

IPC: H01L45/00 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L45/1233 ,  H01L27/2427 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L43/08 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.

公开(公告)号：US20180006219A1

公开(公告)日：2018-01-04

申请号：US15414911

申请日：2017-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hun SEO ,  Jung-Ik OH ,  Yoo-Chul KONG ,  Woo-Ram KIM ,  Jong-Chul PARK ,  Gwang-Hyun BAEK ,  Bok-Yeon WON ,  Hye-Jin CHOI

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L45/1675 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.

公开(公告)号：US20220344331A1

公开(公告)日：2022-10-27

申请号：US17863042

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-Keun LEE ,  Jong-Chul PARK ,  Sang-Hyun LEE

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a first etch stop layer, a second etch stop layer, and an interlayer insulation layer that are stacked on the gate structure, and a contact plug penetrating the interlayer insulation layer, the second etch stop layer, and the first etch stop layer and contacting a sidewall of the gate structure. The contact plug includes a lower portion having a first width and an upper portion having a second width. A lower surface of the contact plug has a stepped shape.

公开(公告)号：US20210249090A1

公开(公告)日：2021-08-12

申请号：US17242712

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul Bee LEE ,  Dong Hun KWAK ,  Jong-Chul PARK

IPC: G11C16/34 ,  G11C16/08

Abstract: A nonvolatile memory device is provided. A nonvolatile memory device comprises a word line, a bit line, a memory cell array including a first memory cell at an intersection region between the word line and the bit line, a word line voltage generating circuitry configured to generate a program voltage, the program voltage to be provided to the word line, a row decoder circuitry configured to receive the program voltage from the word line voltage generating circuitry and configured to provide the program voltage to the word line, a verification circuitry configured to generate a verification signal in response to verifying a success or a failure of programming of the first memory cell, and a control circuitry configured to apply the program voltage to the first memory cell in response to the verification signal, and configured to cut off the program voltage in response to the verification signal.