公开(公告)号：US20230170222A1

公开(公告)日：2023-06-01

申请号：US17842962

申请日：2022-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hoon KWON ,  Chung Ki MIN ,  Bo Un YOON ,  Ki Hoon JANG

IPC: H01L21/306 ,  B24B37/04 ,  B24B57/02

CPC classification number: H01L21/30625 ,  B24B37/042 ,  B24B57/02

Abstract: A method for fabricating a semiconductor device includes providing a polishing pad which includes a first region and a second region separated from each other by a fence, loading a wafer onto the first region, providing a slurry solution onto the first region, providing an ultrapure water onto the second region, turning the polishing pad to polish a surface of the wafer, and unloading the wafer from the polishing pad after polishing on the surface of the wafer is completed, wherein the fence includes a first fence extending from a center of the polishing pad toward an edge of the polishing pad in a first horizontal direction, and a second fence extending from the center of the polishing pad toward the edge of the polishing pad in a second horizontal direction different from the first horizontal direction.

公开(公告)号：US20190157279A1

公开(公告)日：2019-05-23

申请号：US16237913

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbeom PYON ,  Kichul PARK ,  Inkwon KIM ,  Ki Hoon JANG ,  Byoungho KWON ,  Sangkyun KIM ,  Boun YOON

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L27/11286 ,  H01L21/02107 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

公开(公告)号：US20240234164A1

公开(公告)日：2024-07-11

申请号：US18353293

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Keun CHO ,  Dong Hoon KWON ,  Ki Hoon JANG

IPC: H01L21/321 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/3212 ,  H01L21/67103 ,  H01L21/67219 ,  H01L21/67248 ,  H01L21/67706

Abstract: A substrate processing device includes a platen, a polishing pad disposed on the platen, a first rotating body, a second rotating body spaced apart from the first rotating body, a caterpillar module disposed on a portion of the polishing pad and engaged with the first rotating body and the second rotating body, and a temperature controller thermally connected to the caterpillar module.