公开(公告)号：US20170365739A1

公开(公告)日：2017-12-21

申请号：US15410033

申请日：2017-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Won PARK ,  Yong Min KWON ,  Hyung Kun KIM ,  Dong Kuk LEE ,  Dae Yeop HAN

IPC: H01L33/22 ,  H01L33/06 ,  H01L33/32 ,  H01L27/15 ,  H01L33/62 ,  H01L33/54 ,  H01L33/50 ,  H01L33/38 ,  H01L33/00

CPC classification number: H01L33/22 ,  H01L27/153 ,  H01L33/0025 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/325 ,  H01L33/38 ,  H01L33/505 ,  H01L33/54 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0041 ,  H01L2933/005

Abstract: A semiconductor light emitting device package includes a light emitting structure having a first conductive semiconductor layer, an active layer, a second conductive semiconductor layer, a first surface, and a second surface, a first electrode and a second electrode disposed on the second surface of the light emitting structure; an insulating layer, a first metal pad and a second metal pad disposed on the insulating layer, and each having a surface with a first fine uneven pattern so as to have a first surface roughness, a first bonding pad and a second bonding pad disposed on the first metal pad and the second metal pad, respectively, and each having a surface with a second fine uneven pattern so as to have a second surface roughness, and an encapsulant encapsulating the first bonding pad, the second bonding pad, the first metal pad, and the second metal pad.

公开(公告)号：US20150104944A1

公开(公告)日：2015-04-16

申请号：US14276502

申请日：2014-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Won PARK ,  Ju Hyun KIM ,  Yu Seung KIM ,  Sang Yeob SONG ,  Tae Hyun LEE

IPC: H01L21/308

CPC classification number: H01L21/0331 ,  H01L33/10 ,  H01L2933/0016

Abstract: There is provided a method of forming patterns for a semiconductor device. The method sequentially forming a first mask layer and a second mask layer on a substrate. The method also includes forming a second mask pattern layer by patterning the second mask layer. The method further includes forming a first mask pattern layer having a negative slope portion, by etching the first mask layer exposed through the second mask pattern layer. The method also includes forming a thin film layer on the substrate exposed through the first mask pattern layer.

Abstract translation: 提供了一种形成半导体器件的图案的方法。 该方法在衬底上依次形成第一掩模层和第二掩模层。 该方法还包括通过图案化第二掩模层来形成第二掩模图案层。 该方法还包括通过蚀刻通过第二掩模图案层暴露的第一掩模层来形成具有负斜率部分的第一掩模图案层。 该方法还包括在通过第一掩模图案层暴露的衬底上形成薄膜层。