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公开(公告)号：US11658853B2
公开(公告)日：2023-05-23
申请号：US17680583
申请日：2022-02-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Younghwan Chang , Eun-Young Jin , Youngseo Kim , Kilhoon Lee , Hyunwook Lim , Seng-Sub Chun
Abstract: An operation method of a receiver, which includes setting a coefficient of an equalizer based on one of a plurality of first codes, setting a coefficient of an amplifier based on one of a plurality of second codes, performing offset calibration by driving the equalizer and the amplifier based on the coefficient of the equalizer and the coefficient of the amplifier, storing an offset code corresponding to a voltage offset generated when the equalizer and the amplifier are driven, determining whether the offset calibration is completed, performing a normal operation of obtaining reception data from an input signal, in response to determining that the offset calibration is completed, and removing the voltage offset based on the offset code, in the normal operation.
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2.发明授权公开(公告)号：US11996065B2
公开(公告)日：2024-05-28
申请号：US17985599
申请日：2022-11-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyungho Ryu , Kyongho Kim , Yongyun Park , Kilhoon Lee , Yeongcheol Rhee , Taeho Lee , Hyunwook Lim
IPC: G09G5/00
CPC classification number: G09G5/008 , G09G2370/04
Abstract: Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.
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公开(公告)号：US12177324B2
公开(公告)日：2024-12-24
申请号：US18244107
申请日：2023-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Yun Park , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim , Youngmin Choi , Kyungae Kim
IPC: H04L69/324 , H04L47/43
Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.
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公开(公告)号：US11758030B2
公开(公告)日：2023-09-12
申请号：US17679412
申请日：2022-02-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Yun Park , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim , Youngmin Choi , Kyungae Kim
IPC: H04L69/324 , H04L47/43
CPC classification number: H04L69/324 , H04L47/43
Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.
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公开(公告)号：US12132491B2
公开(公告)日：2024-10-29
申请号：US18074775
申请日：2022-12-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyungho Ryu , Yongil Kwon , Kilhoon Lee , Jung-Pil Lim , Hyunwook Lim
CPC classification number: H03L7/091 , G06F1/10 , G11C7/222 , H04L7/0037 , H04L7/0087 , H04L7/033
Abstract: The present disclosure provides methods and apparatuses for correcting skew. In some embodiments, a skew correcting device includes a plurality of samplers configured to sample first data based on a plurality of data clock signals with different phases, and a plurality of edge selectors configured to determine to switch at least one data clock signal of the plurality of data clock signals to an edge clock signal according to a sampling result of the plurality of samplers.
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Patent Agency Ranking
公开(公告)号：US11223468B1
公开(公告)日：2022-01-11
申请号：US17194831
申请日：2021-03-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyungho Ryu , Kyongho Kim , Kilhoon Lee , Yeongcheol Rhee , Taeho Lee , Hyunwook Lim , Younghwan Chang , Sengsub Chun
Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.
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公开(公告)号：US20210067310A1
公开(公告)日：2021-03-04
申请号：US16878728
申请日：2020-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNGPIL LIM , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim
IPC: H04L7/00
Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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公开(公告)号：US11632228B2
公开(公告)日：2023-04-18
申请号：US17476782
申请日：2021-09-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungpil Lim , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim
Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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公开(公告)号：US11133920B2
公开(公告)日：2021-09-28
申请号：US16878728
申请日：2020-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jungpil Lim , Kyungho Ryu , Kilhoon Lee , Hyunwook Lim
Abstract: A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data, packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.
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公开(公告)号：US10763866B2
公开(公告)日：2020-09-01
申请号：US16511733
申请日：2019-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyungho Ryu , Hansu Pae , Kilhoon Lee , Jaeyoul Lee , Jung-Pil Lim , Hyunwook Lim
Abstract: An electronic circuit includes a clock recovery circuit that generates a first reference clock signal based on first reception data and generates a second reference clock signal based on second reception data received after the first reception, a sampling clock generator that generates a sampling clock signal having a phase based on a phase difference between the first reference clock signal and the second reference clock signal, and a sampler that recovers the second reception data based on the generated sampling clock signal.
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