公开(公告)号：US09917589B2

公开(公告)日：2018-03-13

申请号：US15392554

申请日：2016-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghoi Koo ,  Sanghune Park ,  Jin-Ho Choi

IPC: H03K19/00 ,  H03K19/17 ,  G11C7/10 ,  H03K19/0185 ,  H03K19/177 ,  H03K19/0175 ,  H03K19/003

CPC classification number: H03K19/018521 ,  G11C7/10 ,  G11C7/1057 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/017509 ,  H03K19/017518 ,  H03K19/018528 ,  H03K19/018592 ,  H03K19/17744

Abstract: A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

公开(公告)号：US12119049B2

公开(公告)日：2024-10-15

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C7/14 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US20240046982A1

公开(公告)日：2024-02-08

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero KIM ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4096 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US20180175860A1

公开(公告)日：2018-06-21

申请号：US15896280

申请日：2018-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghoi Koo ,  Sanghune Park ,  Jin-Ho Choi

IPC: H03K19/0185 ,  G11C7/10 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/177

CPC classification number: H03K19/018521 ,  G11C7/10 ,  G11C7/1057 ,  H03K19/0013 ,  H03K19/00361 ,  H03K19/017509 ,  H03K19/017518 ,  H03K19/018528 ,  H03K19/018592 ,  H03K19/17744

Abstract: A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

公开(公告)号：US10523204B2

公开(公告)日：2019-12-31

申请号：US15896280

申请日：2018-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghoi Koo ,  Sanghune Park ,  Jin-Ho Choi

IPC: H03K19/00 ,  H03K19/17 ,  H03K19/0185 ,  H03K19/0175 ,  H03K19/003 ,  G11C7/10

Abstract: A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

公开(公告)号：US11830541B2

公开(公告)日：2023-11-28

申请号：US17569679

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/14

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US09007114B2

公开(公告)日：2015-04-14

申请号：US14155692

申请日：2014-01-15

Applicant: Samsung Electronics Co., Ltd

Inventor： Kyunghoi Koo

IPC: H03K3/00 ,  G06F1/04 ,  H03K5/02 ,  H03K5/24

CPC classification number: H03K5/02 ,  H03K5/24

Abstract: A semiconductor device for stably generating a clock signal from a strobe signal includes a processor, a clock signal generation unit receiving a first strobe signal and a second strobe signal to generate the clock signal, and a data reception unit receiving at least one data signal to provide the received data signal to the processor. The clock signal generation unit may comprise a strobe comparator comparing a voltage of a first input terminal with that of a second input terminal to output logic high or logic low, a first switch selectively connecting one of a first and a second signal line to the first input terminal, a second switch selectively connecting one of the second signal line and a reference line to the second input terminal, and a voltage stabilizing circuit pulling up/down at least one of a voltage of the first and the second signal line.

Abstract translation: 用于从选通信号稳定地产生时钟信号的半导体器件包括处理器，接收第一选通信号的时钟信号产生单元和用于产生时钟信号的第二选通信号，以及数据接收单元，接收至少一个数据信号 将接收到的数据信号提供给处理器。 时钟信号生成单元可以包括选通比较器，将第一输入端子的电压与第二输入端子的电压进行比较以输出逻辑高电平或逻辑低电平;第一开关，其选择性地将第一和第二信号线之一连接到第一 输入端子，将第二信号线和参考线中的一个选择性地连接到第二输入端子的第二开关，以及上拉或下拉第一和第二信号线的电压中的至少一个的稳压电路。