公开(公告)号：US11798906B2

公开(公告)日：2023-10-24

申请号：US17551548

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0221 ,  H01L2224/02126 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US09812450B2

公开(公告)日：2017-11-07

申请号：US15006265

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Baek ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Byung-Hee Kim ,  Young-Ju Park ,  Nae-in Lee ,  Kyung-Min Chung

IPC: H01L23/522 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475

Abstract: A semiconductor device includes a plurality of wiring structures spaced apart from each other, and an insulating interlayer structure. Each of the wiring structures includes a metal pattern and a barrier pattern covering a sidewall, a bottom surface, and an edge portion of a top surface of the metal pattern and not covering a central portion of the top surface of the metal pattern. The insulating interlayer structure contains the wiring structures therein, and has an air gap between the wiring structures.

公开(公告)号：US11251144B2

公开(公告)日：2022-02-15

申请号：US16668146

申请日：2019-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US10483224B2

公开(公告)日：2019-11-19

申请号：US15791709

申请日：2017-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US20180138137A1

公开(公告)日：2018-05-17

申请号：US15791709

申请日：2017-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi JIN ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02126 ,  H01L2224/02206 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US20200066666A1

公开(公告)日：2020-02-27

申请号：US16668146

申请日：2019-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US10181525B2

公开(公告)日：2019-01-15

申请号：US15374093

申请日：2016-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Nae-in Lee

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L29/165 ,  H01L21/8234 ,  H01L29/161

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

公开(公告)号：US10153219B2

公开(公告)日：2018-12-11

申请号：US15629072

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-jun Jeon ,  Nae-in Lee ,  Byung-Iyul Park

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/045 ,  H01L23/047 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.