公开(公告)号：US12106794B2

公开(公告)日：2024-10-01

申请号：US18330527

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G06F3/06 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US10885950B2

公开(公告)日：2021-01-05

申请号：US16363077

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US12020767B2

公开(公告)日：2024-06-25

申请号：US17539761

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-Soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C7/222

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US11749338B2

公开(公告)日：2023-09-05

申请号：US17816138

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US11749337B2

公开(公告)日：2023-09-05

申请号：US17807163

申请日：2022-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US09312963B2

公开(公告)日：2016-04-12

申请号：US14552601

申请日：2014-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyoum Kim ,  Seok-Hun Hyun ,  In-Dal Song ,  Seong-Jin Jang ,  Jung-Hwan Choi

IPC: H04B10/50 ,  H04B10/80 ,  H04B10/67 ,  H04B10/572 ,  H04J14/00 ,  H04J14/02

CPC classification number: H04B10/572 ,  H04B10/506 ,  H04B10/671 ,  H04B10/801 ,  H04J14/0278

Abstract: An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.

Abstract translation: 一种光传输转换器，包括：波长选择器，被配置为响应于波长控制信号输出接收波长选择信号和传输波长选择信号;光电转换器，被配置为基于选择光信号将选择光信号转换为接收电信号 接收光信号和接收波长选择信号，以及电光转换器，被配置为基于传输波长选择信号和传输电信号将传输电信号转换为传输光信号。

公开(公告)号：US11244926B2

公开(公告)日：2022-02-08

申请号：US16105202

申请日：2018-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hoon Son ,  Jung-Hwan Choi ,  Seok-Hun Hyun

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

公开(公告)号：US20190304517A1

公开(公告)日：2019-10-03

申请号：US16363077

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Sik Moon ,  Kyung-soo Ha ,  Young-Soo Sohn ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Jin-Hoon Jang ,  Yeon-Kyu Choi ,  Seok-Hun Hyun

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20190237127A1

公开(公告)日：2019-08-01

申请号：US16230185

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20150185812A1

公开(公告)日：2015-07-02

申请号：US14560272

申请日：2014-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hun Hyun ,  Jeong-Kyoum Kim ,  In-Dal Song ,  In-Sung Joe ,  Jung-Hwan Choi ,  Hyun-II Byun ,  Yong-Won Jung

IPC: G06F1/32 ,  G11C11/4074 ,  G11C7/10

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/1054 ,  G11C7/1081 ,  Y02D10/14

Abstract: A memory system includes a memory controller and a memory device. The memory device includes a first converter and a first power controller. The memory device is connected to the memory controller through a channel including at least one optical signal line. The first converter converts between at least one optical signal of the at least one optical signal line and at least one internal electrical signal of the memory device. The first power controller controls power consumption of the first converter based on an operating state of the memory device.

Abstract translation: 存储器系统包括存储器控制器和存储器件。 存储器件包括第一转换器和第一功率控制器。 存储器件通过包括至少一个光信号线的通道连接到存储器控制器。 第一转换器在至少一个光信号线的至少一个光信号与存储器件的至少一个内部电信号之间进行转换。 第一功率控制器基于存储器件的操作状态来控制第一转换器的功耗。