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    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230118906A1

    公开(公告)日：2023-04-20

    申请号：US18085871

    申请日：2022-12-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoontae HWANG ,  Wandon KIM ,  Geunwoo KIM ,  Heonbok LEE ,  Taegon KIM ,  Hanki LEE

    IPC: H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285 ,  H01L29/08 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522

    Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240266402A1

    公开(公告)日：2024-08-08

    申请号：US18393009

    申请日：2023-12-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taegon KIM ,  Jihye YI ,  Yonghee PARK ,  Sanghoon HAN

    IPC: H01L29/15 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/155 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

    Abstract: Provided is a semiconductor device, including a substrate, a first active pattern on the substrate, a first channel pattern on the first active pattern, the first channel pattern including a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern, a first source/drain pattern connected to the first channel pattern, and a gate electrode on the first channel pattern, wherein each of the first semiconductor pattern and the second semiconductor pattern includes a plurality of semiconductor layers, and at least one superlattice layer between adjacent semiconductor layers among the plurality of semiconductor layers, wherein the at least one superlattice layer included in the first semiconductor pattern has a first length, wherein the at least one superlattice layer included in the second semiconductor pattern has a second length, and wherein the first length is greater than the second length.

    SEMICONDUCTOR DEVICE
    8.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240030305A1

    公开(公告)日：2024-01-25

    申请号：US18199133

    申请日：2023-05-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehyun LEE ,  Jonghan LEE ,  Jonghoon BAEK ,  Taegon KIM ,  Yujin JUNG

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78696

    Abstract: The present disclosure provides for semiconductor devices including field effect transistors. In some embodiments, the semiconductor device includes active structures extending in a first direction on a substrate, an isolation pattern formed in a trench between the active structures, gate structures extending in a second direction across the active structures, a cutting insulation pattern formed between end portions of the gate structures in the second direction, and a lower impurity region at an upper portion of the isolation pattern. A first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern. The gate structures are formed on the active structures and the isolation pattern. The lower impurity region contacts at least a portion of the cutting insulation pattern.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220069100A1

    公开(公告)日：2022-03-03

    申请号：US17231126

    申请日：2021-04-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoontae HWANG ,  Wandon KIM ,  Geunwoo KIM ,  Heonbok LEE ,  Taegon KIM ,  Hanki LEE

    IPC: H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L29/66

    Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

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