PLASMA LIGHT DETECTION SYSTEM INCLUDING A SCINTILLATING WINDOW

    公开(公告)号:US20250085445A1

    公开(公告)日:2025-03-13

    申请号:US18633031

    申请日:2024-04-11

    Abstract: A substrate processing apparatus includes a process chamber providing a process space, a stage located in the process chamber and configured to support a substrate, a window coupled to a side of the process chamber, and a scintillator layer coupled to one side surface of the window. The scintillator layer covers a portion of the one side surface of the window which is less than the full window surface. A second surface corresponding to another portion of the one side surface of the window is exposed. Light emitted by a plasma in the process space passes through the window and is collected by an optical system and analyzed. Ultraviolet light passing through the scintillator is converted to longer wavelength, generally visible, light. Comparing the light passing through the bare window with the light passing through the scintillator layer enables analysis of the plasma.

    Position adjusting unit of optical element and maskless exposure apparatus including the same

    公开(公告)号:US10241420B2

    公开(公告)日:2019-03-26

    申请号:US15809293

    申请日:2017-11-10

    Abstract: A position adjusting unit according to some example embodiments includes a base; a mounting part, a driving unit, and a locking part on the base. The mounting part may be movably installed on the base and configured to have an optical element mounted thereto. The driving unit may include a plurality of actuators connected between the base and the mounting part. The driving unit may be configured to move the mounting part with respect to the base. The locking part may be configured to provide a fixing force for fixing a position of the mounting part. The locking part may be configured to release the fixing force when electricity is supplied to the locking part.

    SEMICONDUCTOR DESIGN OPTIMIZATION SYSTEMS AND METHODS OF OPERATION THEREOF

    公开(公告)号:US20240119211A1

    公开(公告)日:2024-04-11

    申请号:US18206278

    申请日:2023-06-06

    CPC classification number: G06F30/392 G06N20/00

    Abstract: A semiconductor design optimization system that includes: a data base configured to store design data, a training data preprocessing unit configured to preprocess the design data and generate training data, a data learning unit configured to generate a physical property prediction model by training using the training data, a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated, and a layout generator configured generate a design layout optimized to distribute the predicted physical property values for each region of the semiconductor device to be fabricated by modifying the design drawings based on the predicted physical property data.

    Memory device including NAND strings and method of operating the same

    公开(公告)号:US10573386B2

    公开(公告)日:2020-02-25

    申请号:US16035958

    申请日:2018-07-16

    Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.

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