-
公开(公告)号:US20250085445A1
公开(公告)日:2025-03-13
申请号:US18633031
申请日:2024-04-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Chansoo Kang , Daewon Kang , Minju Kim , Tae-Hyun Kim , Sang Ki Nam , Dougyong Sung , Jungmo Yang , Sejin Oh , Keonhee Lim , Junho Im
Abstract: A substrate processing apparatus includes a process chamber providing a process space, a stage located in the process chamber and configured to support a substrate, a window coupled to a side of the process chamber, and a scintillator layer coupled to one side surface of the window. The scintillator layer covers a portion of the one side surface of the window which is less than the full window surface. A second surface corresponding to another portion of the one side surface of the window is exposed. Light emitted by a plasma in the process space passes through the window and is collected by an optical system and analyzed. Ultraviolet light passing through the scintillator is converted to longer wavelength, generally visible, light. Comparing the light passing through the bare window with the light passing through the scintillator layer enables analysis of the plasma.
-
2.
公开(公告)号:US10241420B2
公开(公告)日:2019-03-26
申请号:US15809293
申请日:2017-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tae-Hyun Kim , Sang Woo Bae , Sang Don Jang
Abstract: A position adjusting unit according to some example embodiments includes a base; a mounting part, a driving unit, and a locking part on the base. The mounting part may be movably installed on the base and configured to have an optical element mounted thereto. The driving unit may include a plurality of actuators connected between the base and the mounting part. The driving unit may be configured to move the mounting part with respect to the base. The locking part may be configured to provide a fixing force for fixing a position of the mounting part. The locking part may be configured to release the fixing force when electricity is supplied to the locking part.
-
公开(公告)号:US09847422B2
公开(公告)日:2017-12-19
申请号:US15290269
申请日:2016-10-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC: H01L29/78 , H01L21/28 , H01L21/762 , H01L21/8234 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10 , H01L21/308
CPC classification number: H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
-
公开(公告)号:US08969939B2
公开(公告)日:2015-03-03
申请号:US13960434
申请日:2013-08-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC: H01L29/792 , H01L21/8234 , H01L29/78 , H01L27/115 , H01L21/28 , H01L21/762 , H01L29/423 , H01L29/66
CPC classification number: H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。
-
公开(公告)号:US20240119211A1
公开(公告)日:2024-04-11
申请号:US18206278
申请日:2023-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eun-Ho Lee , Jae Choon Kim , Tae-Hyun Kim , Jeong-Hyeon Park , Hwanjoo Park , Sunggu Kang , Sung-Ho Mun
IPC: G06F30/392 , G06N20/00
CPC classification number: G06F30/392 , G06N20/00
Abstract: A semiconductor design optimization system that includes: a data base configured to store design data, a training data preprocessing unit configured to preprocess the design data and generate training data, a data learning unit configured to generate a physical property prediction model by training using the training data, a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated, and a layout generator configured generate a design layout optimized to distribute the predicted physical property values for each region of the semiconductor device to be fabricated by modifying the design drawings based on the predicted physical property data.
-
公开(公告)号:US10716494B2
公开(公告)日:2020-07-21
申请号:US15146336
申请日:2016-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeong-Bin Kim , Se-Hee Lee , Sung-Gook Kim , Tae-Hyun Kim , Soon-Seok Oh , Hyung-Jin Cho
Abstract: A method of providing information according to a gait posture and an electronic device for the same are provided. The method includes collecting sensor values detected using a plurality of sensors located at the surrounding of a user's feet, determining a user's gait posture by using the detected sensor values, and outputting at least one of information on the user's gait posture, information on muscle fatigue of the user according to the gait, information on joint fatigue of the user according to the gait, and information on a recommended exercise for the user based on the determined user's gait posture.
-
公开(公告)号:US09263588B2
公开(公告)日:2016-02-16
申请号:US14635034
申请日:2015-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC: H01L29/78 , H01L21/28 , H01L21/762 , H01L21/8234 , H01L27/115 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10
CPC classification number: H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
-
公开(公告)号:US09601209B2
公开(公告)日:2017-03-21
申请号:US14716550
申请日:2015-05-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Tae-Hyun Kim , Young-Sun Min , Sung-Whan Seo , Won-Tae Kim , Sang-Wan Nam
CPC classification number: G11C16/26 , G11C5/147 , G11C7/04 , G11C16/30 , G11C16/349 , G11C29/021 , G11C29/028 , H02M3/158
Abstract: A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.
-
公开(公告)号:US20160155838A1
公开(公告)日:2016-06-02
申请号:US15006522
申请日:2016-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
CPC classification number: H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
-
公开(公告)号:US10573386B2
公开(公告)日:2020-02-25
申请号:US16035958
申请日:2018-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wan-Dong Kim , Tae-Hyun Kim , Sang-Wan Nam , Sang-Soo Park , Jae-Yong Jeong
IPC: G11C16/04 , G11C16/08 , G11C16/28 , G11C16/10 , G11C16/26 , G11C16/34 , G11C11/56 , G11C16/32 , G11C5/06
Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.
-
-
-
-
-
-
-
-
-