公开(公告)号：US20170040221A1

公开(公告)日：2017-02-09

申请号：US15196870

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol KIM ,  Dong-Hoon KHANG ,  Do-Hyoung KIM ,  Seung-Jin MUN ,  Yong-Joon CHOI ,  Seung-Mo HA

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3115

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/0275 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31155 ,  H01L29/66795

Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.

Abstract translation: 制造半导体器件的方法包括在复合膜上形成复合膜，形成粗糙图案，通过使粗糙图案经受离子注入和等离子体处理形成平滑图案，并使用平滑图案将复合膜图案化为第一 面具。

公开(公告)号：US20160247925A1

公开(公告)日：2016-08-25

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US20160064380A1

公开(公告)日：2016-03-03

申请号：US14934119

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US20150162247A1

公开(公告)日：2015-06-11

申请号：US14531987

申请日：2014-11-03

Applicant: SAMSUNG ELECTRONICS CO., Ltd.

Inventor： Yong-Joon CHOI ,  MYEONGCHEOL KIM ,  CHEOL KIM ,  GeumJung SEONG ,  Hak-Sun LEE ,  Haegeon JUNG ,  Ji-Eun HAN

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76224 ,  H01L27/0886

Abstract: The disclosure provides semiconductor devices and methods of manufacturing the same. The method includes etching a substrate using a first mask pattern formed on the substrate to form a trench, forming a preliminary device isolation pattern filling the trench and including first and second regions having first thicknesses, forming a second mask pattern on the first region, etching an upper portion of the second region and a portion of the first mask pattern, which are exposed by the second mask pattern, to form a second region having a second thickness smaller than the first thickness, removing the first and second mask patterns, and etching upper portions of the first region and the second region having the second thickness to form a device isolation pattern defining preliminary fin-type active patterns. An electronic device including a semiconductor device and a manufacturing method thereof are also disclosed.

Abstract translation: 本公开提供半导体器件及其制造方法。 该方法包括使用形成在衬底上的第一掩模图案来蚀刻衬底以形成沟槽，形成填充沟槽的初步器件隔离图案，并且包括具有第一厚度的第一和第二区域，在第一区域上形成第二掩模图案，蚀刻 第二区域的上部和第一掩模图案的一部分被第二掩模图案曝光，以形成具有小于第一厚度的第二厚度的第二区域，去除第一和第二掩模图案，以及蚀刻 所述第一区域的上部和所述第二区域具有第二厚度，以形成限定预备鳍型活性图案的器件隔离图案。 还公开了一种包括半导体器件及其制造方法的电子器件。