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公开(公告)号：US10342724B2
公开(公告)日：2019-07-09
申请号：US14634403
申请日：2015-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byungjune Choi , Yongjae Kim , Youn Baek Lee , Jeonghun Kim , Se-Gon Roh , Minhyung Lee , Jongwon Lee , Hyun Do Choi , Youngdo Kwon , ByungKwon Choi
Abstract: In a joint assembly of a walking assistance robot that is capable of performing an operation with 3 degrees of freedom, similarly to a user's joint, a rolling motion and a sliding motion are simultaneously made, and a rotation center changes so that the joint assembly can make a similar motion to that of an actual knee joint of the user. Thus, when the user wears the walking assistance robot and walks, misalignment can be prevented from occurring in the knee joint.
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公开(公告)号：US12089420B2
公开(公告)日：2024-09-10
申请号：US18312977
申请日：2023-05-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung Pil Ko , Yongjae Kim
Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.
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公开(公告)号：US10070982B2
公开(公告)日：2018-09-11
申请号：US14599804
申请日：2015-01-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae Kim , Youn Baek Lee , Jongwon Lee , Byungjune Choi , Jeonghun Kim , Se-Gon Roh , Minhyung Lee , Hyun Do Choi , Sunggu Kwon , Youngdo Kwon
CPC classification number: A61F5/0102 , A01D34/90 , A61F2/60 , A61F2/68 , A61F5/01 , A61F5/32 , A61F2005/0141 , A61F2220/0091 , A61H1/02 , A61H1/024 , A61H1/0244 , A61H3/00 , A61H2003/007 , A61H2201/0192 , A61H2201/1207 , A61H2201/163 , A61H2201/1642 , A61H2201/165 , B25J9/00 , Y10T74/20207
Abstract: A frame configured of a plurality of links pivotally connected to one another is flexibly bent, and pins that connect the plurality of links that constitute the frame are inserted into and slide in a curve-shaped slot and a slot in a vertical direction so that, even though the frame is bent, the entire length of the frame is increased and ends of the frame can be moved along a straight line that is horizontal with respect to the ground.
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公开(公告)号：US12112783B2
公开(公告)日：2024-10-08
申请号：US17537937
申请日：2021-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung Pil Ko , Yongjae Kim , Geonhee Bae , Gawon Lee , Kilho Lee
CPC classification number: G11C11/161 , H01L23/528 , H10B61/00 , H10N50/10 , H10N50/20 , H10N50/80 , H10N50/85
Abstract: A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.
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公开(公告)号：US20230309322A1
公开(公告)日：2023-09-28
申请号：US18312977
申请日：2023-05-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung Pil Ko , Yongjae Kim
Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.
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Patent Agency Ranking
公开(公告)号：US20210242396A1
公开(公告)日：2021-08-05
申请号：US17083943
申请日：2020-10-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae Kim , Kuhoon Chung , Gwanhyeob Koh , Bae-Seong Kwon , Kyungtae Nam
Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.
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公开(公告)号：US20240431119A1
公开(公告)日：2024-12-26
申请号：US18405141
申请日：2024-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kilho Lee , Yongjae Kim , Junho Park
IPC: H10B61/00
Abstract: A semiconductor device may include a lower dielectric layer on a substrate, data storage patterns on the lower dielectric layer and spaced apart from each other in first and second directions, a cell dielectric layer on the lower dielectric layer and on the data storage patterns, voids in the cell dielectric layer and between ones of the data storage patterns, upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first and second directions, and upper conductive lines on the upper conductive contacts and spaced apart from each other in the second direction and extending in the first direction. Each of the upper conductive lines may be electrically connected to respective ones of the upper conductive contacts. The respective ones of the upper conductive contacts may be spaced apart from each other in the first direction.
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公开(公告)号：US12058941B2
公开(公告)日：2024-08-06
申请号：US17083943
申请日：2020-10-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae Kim , Kuhoon Chung , Gwanhyeob Koh , Bae-Seong Kwon , Kyungtae Nam
Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.
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9.发明申请公开(公告)号：US20240387168A1
公开(公告)日：2024-11-21
申请号：US18624788
申请日：2024-04-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinwoo Park , Heeyeop Chae , Yongjae Kim , Sangwuk Park , Yuna Lee , Jihye Lee , Jungpyo Hong
IPC: H01L21/02 , C23C16/44 , H01L21/311
Abstract: A method of manufacturing a semiconductor element includes placing a structure, the structure including a substrate and a first metal-containing film disposed on the substrate, fluorinating at least one atomic layer from an exposed surface of the first metal-containing film by supplying a fluorinating gas to the structure to form a fluorinated atomic layer, and etching the fluorinated atomic layer of the first metal-containing film by supplying an etching gas to the structure, wherein the etching gas includes an inert gas in a plasma state.
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公开(公告)号：US20240349621A1
公开(公告)日：2024-10-17
申请号：US18752866
申请日：2024-06-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongjae Kim , Kuhoon Chung , Gwanhyeob Koh , Bae-Seong Kwon , Kyungtae Nam
Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.
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