公开(公告)号：US20220028827A1

公开(公告)日：2022-01-27

申请号：US17187985

申请日：2021-03-01

申请人： Samsung Electronics Co., Ltd.

发明人： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L25/065 ,  H01L23/64 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528

摘要： A semiconductor device includes an interposer substrate and at least one die mounted on the interposer substrate. The interposer substrate includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, an interlayer insulating layer on the first surface of the semiconductor substrate, a capacitor in a hole penetrating the interlayer insulating layer, an interconnection layer on the interlayer insulating layer, and a through-via extending from the interconnection layer toward the second surface of the semiconductor substrate in a vertical direction that is perpendicular to the first surface of the semiconductor substrate. The capacitor includes a sequential stack of a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode. A bottom of the hole is distal from the second surface of the semiconductor substrate in relation to the first surface of the semiconductor substrate.

公开(公告)号：US20230230944A1

公开(公告)日：2023-07-20

申请号：US17959352

申请日：2022-10-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Boin NOH ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/73 ,  H01L24/08 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2924/3511 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/73253 ,  H01L2224/08148 ,  H01L2224/05655 ,  H01L2224/05541 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05573 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166

摘要： A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.

公开(公告)号：US20210118696A1

公开(公告)日：2021-04-22

申请号：US15931738

申请日：2020-05-14

申请人： Samsung Electronics Co., Ltd.

发明人： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L21/48 ,  H05K3/10

摘要： The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.

公开(公告)号：US20240164081A1

公开(公告)日：2024-05-16

申请号：US18405736

申请日：2024-01-05

申请人： Samsung Electronics Co., Ltd.

发明人： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B12/00

CPC分类号： H10B10/18 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/50

摘要： A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.

公开(公告)号：US20220328404A1

公开(公告)日：2022-10-13

申请号：US17527230

申请日：2021-11-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L23/528 ,  H01L25/065 ,  H01L23/522 ,  H01L23/48 ,  H01L21/768

摘要： A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.

公开(公告)号：US20210125937A1

公开(公告)日：2021-04-29

申请号：US16876502

申请日：2020-05-18

申请人： Samsung Electronics Co., Ltd.

发明人： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L23/544 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498 ,  H01L25/00

摘要： A method of fabricating a semiconductor device comprises forming first and second align keys in a wafer, the second align key apart from the first align key, forming third and fourth align keys in the wafer, the third align key apart from the second align key, the fourth align key apart from the third align key, forming a fifth align key in the wafer, the fifth align key apart from the fourth align key, forming a first line pattern in the wafer using the second and third align keys, forming a second line pattern in the wafer using the fourth and fifth align keys, forming a first interposer including the first line pattern by cutting a space between the first and second align keys, and forming a second interposer, the second interposer including the second line pattern by cutting a space between the third and fourth align keys.

公开(公告)号：US20230317539A1

公开(公告)日：2023-10-05

申请号：US17986995

申请日：2022-11-15

申请人： Samsung Electronics Co., Ltd.

发明人： Bo In NOH ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/3135 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L23/315 ,  H01L23/49822 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2224/73204 ,  H01L2224/16014 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/186 ,  H01L2224/3201 ,  H01L2224/32055 ,  H01L2224/32053 ,  H01L2224/32059 ,  H01L23/49816 ,  H01L25/0655

摘要： A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

公开(公告)号：US20230131382A1

公开(公告)日：2023-04-27

申请号：US17843594

申请日：2022-06-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Shaofeng DING ,  Jihyung KIM ,  Won Ji PARK ,  Jeong Hoon AHN ,  Jaehee OH ,  Yun Ki CHOI

IPC分类号： H01L27/06 ,  H01L25/07 ,  H01L27/02

摘要： Disclosed is a three-dimensional integrated circuit structure including an active device die and a capacitor die stacked on the logic die. The active device die includes: a first substrate including a front side and a back side that are opposite to each other; a power delivery network on the back side of the first substrate; a device layer on the front side of the first substrate; a first wiring layer on the device layer; and a through contact that vertically extends from the power delivery network to the first wiring layer. The passive device die includes: a second substrate including a front side and a back side that are opposite to each other, the front side of the second substrate facing the front side of the first substrate; an interlayer dielectric layer on the front side of the second substrate, the interlayer dielectric layer including at least one hole; a passive device in the hole; and a second wiring layer on the passive device, wherein the second wiring layer faces and is connected to the first wiring layer.

公开(公告)号：US20230099844A1

公开(公告)日：2023-03-30

申请号：US17830488

申请日：2022-06-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yong Ho KIM ,  Woo Jin JANG ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L23/00 ,  H01L25/065

摘要： Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.

公开(公告)号：US20220271045A1

公开(公告)日：2022-08-25

申请号：US17474436

申请日：2021-09-14

申请人： Samsung Electronics Co., Ltd.

发明人： Shaofeng DING ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.