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公开(公告)号：US20170078189A1
公开(公告)日：2017-03-16
申请号：US15132663
申请日：2016-04-19
发明人： Sungju HAN , Jinho LEE , Kiyoung CHOI , Woong SEO
IPC分类号： H04L12/733 , H04L12/44 , H04L12/741
CPC分类号： H04L45/20 , H04L12/44 , H04L12/5692 , H04L45/121 , H04L45/122 , H04L45/74 , H04L49/109 , H04L49/25
摘要： Provided is a multi network and method to transmit packets. The multi network includes a mesh network, a tree network, and a network interface connected to the mesh network and the tree network and configured to transmit, through the mesh network and the tree network, a packet generated by a processing unit, of a processing system having plural processing units, at a starting point to a destination point for another processing unit of the processing system and configured to selectively inject the packet into one of the mesh network and the tree network to transmit the packet to the other processing unit.
摘要翻译： 提供了一种传输数据包的多网络和方法。 多网络包括网状网络，树形网络和连接到网状网络和树状网络的网络接口，并且被配置为通过网状网络和树状网络将由处理单元生成的分组发送到处理 系统具有多个处理单元，在处理系统的另一个处理单元的目的地点的起点处，并且被配置为选择性地将分组注入到网状网络和树形网络之一中以将分组发送到另一个处理单元。
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公开(公告)号：US20160232093A1
公开(公告)日：2016-08-11
申请号：US15019368
申请日：2016-02-09
发明人： Namhyung KIM , Junwhan AHN , Kiyoung CHOI , Woong SEO
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0862 , G06F2212/6026 , G06F2212/604
摘要： A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.
摘要翻译： 管理高速缓存的方法包括将较高级别高速缓存的第一数据存储在下级高速缓存中，基于关于第一数据的访问信息来预测与第一数据具有相同签名的第二数据的重用距离级别，并存储第二数据 基于第二数据的预测的再利用距离级别，下级缓存和主存储器之一中的数据。
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公开(公告)号：US20150331719A1
公开(公告)日：2015-11-19
申请号：US14800002
申请日：2015-07-15
发明人： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU , Seok-Woo SONG , JOHN Dongjun KIM , Min-Seok LEE
IPC分类号： G06F9/50
CPC分类号： G06F9/505 , G06F9/46 , G06F9/4881 , G06F2209/5022
摘要： An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.
摘要翻译： 提供了一种装置和作业调度方法。 例如，该装置是多核处理装置。 该装置和方法通过动态地管理分配给设备的每个核心的最大数量的作业来最小化共享资源所引起的核心性能下降。 所述设备包括至少一个核心，其包括被配置为存储多个活动周期的活动周期计数单元和被配置为存储多个失速周期的失速循环计数单元，以及作业调度器，其被配置为将至少一个作业分配给 至少一个核心，基于活动周期的数量和失速周期的数量。 当停顿周期数与核心的活动周期数之比太大时，作业调度程序为该核心分配较少的作业以提高性能。
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公开(公告)号：US20150143383A1
公开(公告)日：2015-05-21
申请号：US14606395
申请日：2015-01-27
发明人： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU , Seok-Woo SONG , JOHN Dongjun KIM , Min-Seok LEE
IPC分类号： G06F9/50
CPC分类号： G06F9/505 , G06F9/46 , G06F9/4881 , G06F2209/5022
摘要： An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.
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公开(公告)号：US20180122041A1
公开(公告)日：2018-05-03
申请号：US15618685
申请日：2017-06-09
发明人： Woong SEO , Santosh George ABRAHAM
CPC分类号： G06T1/60 , G06T1/20 , G06T15/005
摘要： A method of managing graphics data in a graphics processing device may include: receiving a first draw call having a first identifier, generating a first lookup table having the first identifier mapped in association with a first handle value by allocating the first handle value to the first identifier, generating a second lookup table having the first handle value mapped in association with a first graphics state setting value by allocating the first handle value to the first graphics state setting value, wherein the first graphics state setting value corresponds to the first identifier, and performing at least one graphics pipeline operation to process the first draw call by using the first graphics state setting value obtained from the second lookup table.
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公开(公告)号：US20170256024A1
公开(公告)日：2017-09-07
申请号：US15420459
申请日：2017-01-31
发明人： Santosh ABRAHAM , Karthik RAMANI , Woong SEO , Kwontaek KWON , Jeongae PARK
IPC分类号： G06T1/60 , H04N19/426 , H04N19/44 , G06T7/40
CPC分类号： G06T1/60 , G06T15/005 , G06T15/04 , H04N19/426 , H04N19/44 , Y02D10/13
摘要： A texture cache architecture facilitates access of compressed texture data in non-power of two formats, such as the Adaptive Scalable Texture Compression (ASTC) codec. In one implementation, the texture cache architecture includes a controller, a first buffer, a second buffer, and a texture decompressor. A first buffer stores one or more blocks of compressed texel data fetched, in response to a first request, from a first texture cache, where the one or more blocks of compressed texel data including at least requested texel data. The second buffer stores decompressed one or more blocks of compressed texel data and provides the decompressed requested texel data as output to a second texture cache. The one or more blocks of compressed texel data stored by the first buffer includes second texel data in addition to the requested texel data.
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7.发明申请PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF 审中-公开支持多模和多模支持方法的处理器公开(公告)号：US20140215193A1
公开(公告)日：2014-07-31
申请号：US14165881
申请日：2014-01-28
发明人： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU
IPC分类号： G06F9/30
CPC分类号： G06F15/8015 , G06F9/30058 , G06F9/3804 , G06F9/3851 , G06F9/3887 , G06F9/3889
摘要： Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.
摘要翻译： 实施例包括能够支持多模式和相应方法的处理器。 处理器包括前端单元，多个前端单元的多个处理元件; 以及控制器，被配置为确定是否由于条件分支而发生线程发散。 如果存在线程发散，则处理器可以设置控制信息以使用当前激活的前端单元来控制处理元件。 如果没有，则处理器可以使用当前激活的前端单元来设置控制信息以控制处理元件。
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公开(公告)号：US20170032543A1
公开(公告)日：2017-02-02
申请号：US15098786
申请日：2016-04-14
发明人： Yeongon CHO , Seok KANG , Soojung RYU , Jeongae PARK , Woong SEO , Sangheon LEE
CPC分类号： G06T11/001 , G06T1/20 , G06T1/60 , G06T15/005 , G06T15/04
摘要： A texture processor includes: a texture cache configured to store textures; a controller configured to determine a texture address corresponding to a requested texture among the stored textures and read a texture corresponding to the texture address from the texture cache; a format converter configured to convert a format of the read texture into another format, based on a degree of texture precision required by a graphics processing unit (GPU); and a texture filter configured to perform texture filtering using the read texture having its format converted into the another format.
摘要翻译： 纹理处理器包括：纹理缓存，被配置为存储纹理; 控制器，被配置为确定所存储的纹理中与所请求的纹理相对应的纹理地址，并从纹理高速缓存读取与纹理地址相对应的纹理; 格式转换器，其被配置为基于图形处理单元（GPU）所需的纹理精度来将所读取的纹理的格式转换成另一种格式; 以及纹理滤波器，其被配置为使用其格式转换成另一格式的读取纹理来执行纹理滤波。
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公开(公告)号：US20160124866A1
公开(公告)日：2016-05-05
申请号：US14715683
申请日：2015-05-19
发明人： Seong Hoon JEONG , Woong SEO , Sang Heon LEE , Sun Min KWON , Ho Young KIM , Hee Jun SHIM
CPC分类号： G06F12/0207 , G06F12/0607 , G06F12/0846 , G06F2212/1016 , G06F2212/1056 , G06F2212/455
摘要： A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.
摘要翻译： 提供了缓存存储器及其管理方法。 管理高速缓冲存储器的方法包括：确定存储在存储体中的数据带宽的位的数量是要存储的数据中的单位数据的位数的整数倍，存储第一单位数据 响应于不是单位数据的位数的整数倍的数据带宽的比特数，存储在存储体中的第一地址的第一区域中，并存储部分第二单位数据 被存储在第一地址的第二区域中。
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公开(公告)号：US20150227490A1
公开(公告)日：2015-08-13
申请号：US14694420
申请日：2015-04-23
发明人： Woong SEO , Han-Joon KIM , John KIM , Soo-Jung RYU
CPC分类号： G06F15/80 , G06F9/44505 , G06F15/17312 , H04L45/06 , H04L45/60
摘要： Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.
摘要翻译： 提供了具有优异性能和效率的数据传输结构的处理器。 根据一个方面，处理器可以包括多个处理元件，分别连接到处理元件的多个路由器，以及形成在路由器之间的多个连接链路，使得数据经由网络在处理器之间传送。
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