公开(公告)号：US09530506B2

公开(公告)日：2016-12-27

申请号：US14550897

申请日：2014-11-21

Applicant: SanDisk Technologies Inc.

Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

IPC: G11C7/00 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

Abstract translation: 描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。 存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。 在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。 在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时 存储器阵列和存储器阵列内的未选择字线组的位置。

公开(公告)号：US20160358933A1

公开(公告)日：2016-12-08

申请号：US14733335

申请日：2015-06-08

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Peter Rabkin ,  Jayavel Pachamuthu ,  Johann Alsmeier ,  Masaaki Higashitani

IPC: H01L27/115 ,  H01L29/12 ,  H01L29/45 ,  H01L21/324 ,  H01L21/28 ,  H01L29/205 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02546 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7926

Abstract: A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Abstract translation: 限制在二维圆柱形区域内的圆柱形约束电子气体可以形成在延伸穿过包括控制栅电极的多个导电层的垂直半导体沟道中。 存储器开口中的记忆膜插入在垂直半导体沟道和导电层之间。 垂直半导体沟道包括较宽的带隙半导体材料和窄带隙半导体材料。 在较宽带隙半导体材料和窄带隙半导体材料之间的界面处形成圆柱形约束电子气。 作为二维电子气体，圆柱形约束电子气体可以为垂直半导体通道提供高电荷载流子迁移率，其可有利地用于为三维存储器件提供更高的性能。

公开(公告)号：US09443597B2

公开(公告)日：2016-09-13

申请号：US14669267

申请日：2015-03-26

Applicant: SanDisk Technologies Inc.

Inventor： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

IPC: G11C16/16 ,  G11C16/14 ,  G11C7/10 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C7/1006 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

Abstract: A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping between the select gates and the dummy storage elements.

Abstract translation: 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于选择栅极和虚拟存储元件之间的电荷捕获减少，存储元件的写擦除耐久性增加。

公开(公告)号：US09425299B1

公开(公告)日：2016-08-23

申请号：US14733244

申请日：2015-06-08

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Peter Rabkin ,  Jayavel Pachamuthu ,  Johann Alsmeier ,  Masaaki Higashitani

IPC: H01L29/778 ,  H01L27/115 ,  H01L29/205 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/7783 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/205 ,  H01L29/513 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7833 ,  H01L29/7889

Abstract: A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.

Abstract translation: 限制在二维圆柱形区域内的圆柱形约束电子气体可以形成在延伸穿过包括控制栅电极的多个导电层的垂直半导体沟道中。 存储器开口中的记忆膜插入在垂直半导体沟道和导电层之间。 垂直半导体沟道包括较宽的带隙半导体材料和窄带隙半导体材料。 在较宽带隙半导体材料和窄带隙半导体材料之间的界面处形成圆柱形约束电子气。 作为二维电子气体，圆柱形约束电子气体可以为垂直半导体通道提供高电荷载流子迁移率，其可有利地用于为三维存储器件提供更高的性能。

公开(公告)号：US09418751B1

公开(公告)日：2016-08-16

申请号：US14808329

申请日：2015-07-24

Applicant: SanDisk Technologies Inc.

Inventor： Deepanshu Dutta ,  Shota Murai ,  Hideto Tomiie ,  Masaaki Higashitani

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C11/34

CPC classification number: G11C16/34 ,  G11C11/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/028

Abstract: A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate transistors is evaluated, such as in response to a program, erase or read command involving a block or sub-block of memory cells. For example, a lower tail and an upper tail of the Vth distribution can be evaluated using read voltages. If the Vth is out-of-range, such as due to read disturb, data retention loss or defects in the memory device, the block or sub-block is marked as being bad and previously-programmed data in the block or sub-block can be copied to another location. If the Vth is in range, the command can be executed. Also, a control gate voltage for the select gate transistors can be set based on a Vth metric which is obtained from the evaluation.

Abstract translation: 存储器件包括布置在选择栅晶体管之间的NAND串中的存储器单元。 评估选择栅极晶体管的阈值电压（Vth）分布，例如响应于涉及存储器单元的块或子块的程序，擦除或读取命令。 例如，可以使用读取电压来评估Vth分布的下尾和上尾。 如果Vth超出范围，例如由于读取干扰，数据保留丢失或存储器件中的缺陷，则块或子块被标记为块或子块中的先前编程的数据 可以复制到另一个位置。 如果Vth在范围内，则可以执行命令。 此外，可以基于从评估获得的Vth度量来设置用于选择栅极晶体管的控制栅极电压。

公开(公告)号：US20160148691A1

公开(公告)日：2016-05-26

申请号：US14550897

申请日：2014-11-21

Applicant: SanDisk Technologies Inc.

Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

IPC: G11C16/10

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

Abstract translation: 描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。 存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。 在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。 在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时 存储器阵列和存储器阵列内的未选择字线组的位置。

公开(公告)号：US09312015B1

公开(公告)日：2016-04-12

申请号：US14523848

申请日：2014-10-25

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Chia-Lin Hsiung ,  Fumiaki Toyama ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H01L27/0207 ,  H01L27/11529

Abstract: Methods for reducing an increase in the threshold voltage of a transistor due to the body effect and increasing the junction breakdown voltage for junctions of the transistor are described. The transistor may comprise an NMOS transistor that transfers a programming voltage (e.g., 24V) to a word line of a memory array during a programming operation. In some cases, a first poly shield may be positioned within a first distance of a gate of the transistor and may comprise a first polysilicon structure that is directly adjacent to the gate of the transistor. The first poly shield may be arranged in a first direction (e.g., in the channel length direction of the transistor). The first poly shield may be biased to a first voltage greater than ground (e.g., 10V) during the programming operation to reduce an increase in the threshold voltage of the transistor due to the body effect.

Abstract translation: 描述了用于减小由于体效应引起的晶体管阈值电压增加并增加晶体管结的结击穿电压的方法。 晶体管可以包括在编程操作期间将编程电压（例如，24V）传送到存储器阵列的字线的NMOS晶体管。 在一些情况下，第一多晶硅屏蔽可以位于晶体管的栅极的第一距离内，并且可以包括与晶体管的栅极直接相邻的第一多晶硅结构。 第一多晶硅屏蔽可以沿第一方向（例如，在晶体管的沟道长度方向）上布置。 在编程操作期间，第一多晶屏蔽可被偏压到大于接地（例如10V）的第一电压，以减少由于身体效应引起的晶体管的阈值电压的增加。

公开(公告)号：US20160099066A1

公开(公告)日：2016-04-07

申请号：US14503987

申请日：2014-10-01

Applicant: SanDisk Technologies Inc.

Inventor： Mohan Vamsi Dunga ,  Masaaki Higashitani

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582

Abstract: Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.

Abstract translation: 这里公开了在编程存储器单元时预先给通道预充电的技术。 在通道预充电阶段期间，将预充电电压施加到两个所选择的位线和禁止的位线。 预充电电压被传递到NAND串的通道。 禁止位线上的电压然后减小到编程禁止电压。 此外，所选位线上的电压降低到程序使能电压。 此外，来自所选择的NAND串的通道的预充电电压被放电，同时保持禁止的NAND串的通道中的预充电电压。 然后可以提高禁止的NAND串的通道中的电位，并且可以将编程电压施加到所选择的字线。

公开(公告)号：US09123425B2

公开(公告)日：2015-09-01

申请号：US14047381

申请日：2013-10-07

Applicant: SanDisk Technologies Inc.

Inventor： Yingda Dong ,  Masaaki Higashitani

IPC: G11C16/04 ,  G11C16/12 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  H01L27/115 ,  H01L29/49

CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4983

Abstract: In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided.

Abstract translation: 在3D堆叠的非易失性存储器件中，多个更小的漏极端选择栅极（SGD）晶体管代替一个较大的SGD晶体管。 SGD晶体管具有不同的控制栅极过驱动电压，使得在编程操作期间，在禁止的NAND串中产生不连续的沟道电位。 最靠近位线的SGD晶体管具有较低的控制栅极过驱动电压，使得其下的沟道电位较低，并且下一个SGD晶体管具有较高的控制栅极过驱动电压，使得其下的沟道电位较高。 可以通过编程不同的阈值电压或通过为SGD晶体管提供不同的控制栅极电压来提供不同的控制栅极过驱动电压。 可以避免由于漏极引起的屏障降低导致的Vsgd窗口的不期望的减少。

公开(公告)号：US20150200014A1

公开(公告)日：2015-07-16

申请号：US14669267

申请日：2015-03-26

Applicant: SanDisk Technologies Inc.

Inventor： Deepanshu Dutta ,  Mohan Dunga ,  Masaaki Higashitani

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C7/1006 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16

Abstract: A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping between the select gates and the dummy storage elements.

Abstract translation: 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于选择栅极和虚拟存储元件之间的电荷捕获减少，存储元件的写擦除耐久性增加。