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公开(公告)号：US20170047339A1
公开(公告)日：2017-02-16
申请号：US14825433
申请日：2015-08-13
发明人： Raul Adrian Cernea
IPC分类号： H01L27/115 , H01L23/532 , H01L21/768
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/31144 , H01L21/32139 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/53257 , H01L23/53271 , H01L27/11524 , H01L29/4916
摘要： A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.
摘要翻译： 3D存储器具有堆叠在衬底顶部上的多个存储层。 不同存储层中的字线分别连接到多个存储器层下方的衬底中不同的接触焊盘列。 通过在每个接触焊盘上方创建垂直位移并创建连接到接触焊盘的垂直字线VIA来实现连接。 对于给定的存储器层及其垂直字线VIA的列，在每个垂直字线VIA和相邻字线之间形成向下到存储器层的辅助垂直轴。 辅助垂直轴与允许进入垂直字线VIA的垂直移动相邻。 辅助垂直轴还能够挖掘字线和垂直字线VIA之间的横向空间。 用导电材料填充空间完成从字线到接触垫的导电路径。
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2.发明申请3D Memory Having Vertical Switches with Surround Gates and Method Thereof 审中-公开具有带环绕门的垂直开关的3D存储器及其方法公开(公告)号：US20170040381A1
公开(公告)日：2017-02-09
申请号：US15331443
申请日：2016-10-21
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/04 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.
摘要翻译： 3D存储器件的垂直切换层用于将一组垂直局部位线切换到相应的全局位线集合，垂直切换层是垂直薄膜晶体管（TFT）的TFT通道的2D阵列，其与 连接到本地位线阵列，每个TFT将局部位线切换到相应的全局位线。 阵列中的TFT分别具有沿着x轴和y轴的长度Lx和Ly的间隔，使得栅极材料层在xy平面内围绕每个TFT形成环绕栅，并且具有合并以形成行选择的厚度 沿x轴线，同时保持单独行选择线之间的长度Ls的间隔。 环绕栅极提高了TFT的开关容量。
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公开(公告)号：US09881676B1
公开(公告)日：2018-01-30
申请号：US15290818
申请日：2016-10-11
发明人： Jong Hak Yuh , Raul Adrian Cernea , Seungpil Lee , Yen-Lung Jason Li , Qui Nguyen , Tai-Yuan Tseng , Cynthia Hsu
摘要： Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.
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公开(公告)号：US09825048B2
公开(公告)日：2017-11-21
申请号：US14825433
申请日：2015-08-13
发明人： Raul Adrian Cernea
IPC分类号： H01L27/115 , H01L21/768 , H01L23/532 , H01L27/11556 , H01L27/11524 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L29/49
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/31144 , H01L21/32139 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/53257 , H01L23/53271 , H01L27/11524 , H01L29/4916
摘要： A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.
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