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公开(公告)号：US20180322928A1
公开(公告)日：2018-11-08
申请号：US15589120
申请日：2017-05-08
发明人： Kenneth Louie , Qui Nguyen , Tai-yuan Tseng , Jong Yuh , Ohwon Kwon
摘要： This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.
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公开(公告)号：US10255978B2
公开(公告)日：2019-04-09
申请号：US15589120
申请日：2017-05-08
发明人： Kenneth Louie , Qui Nguyen , Tai-yuan Tseng , Jong Yuh , Ohwon Kwon
摘要： This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic.
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公开(公告)号：US09881676B1
公开(公告)日：2018-01-30
申请号：US15290818
申请日：2016-10-11
发明人： Jong Hak Yuh , Raul Adrian Cernea , Seungpil Lee , Yen-Lung Jason Li , Qui Nguyen , Tai-Yuan Tseng , Cynthia Hsu
摘要： Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.
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公开(公告)号：US10892021B2
公开(公告)日：2021-01-12
申请号：US16216719
申请日：2018-12-11
发明人： Qui Nguyen , Arka Ganguly
IPC分类号： G11C16/30 , G11C16/10 , G11C16/26 , G11C16/16 , G11C16/08 , G11C16/04 , H01L27/11556 , H01L27/11582
摘要： Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.
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公开(公告)号：US20180197586A1
公开(公告)日：2018-07-12
申请号：US15625848
申请日：2017-06-16
发明人： Qui Nguyen , Alexander Chu , Kenneth Louie , Anirudh Amarnath , Jixin Yu , Yen-Lung Jason Li , Tai-Yuan Tseng , Jong Yuh
IPC分类号： G11C8/08 , G11C5/06 , H01L27/112 , G11C8/10 , G06F13/40
CPC分类号： G11C8/08 , G06F13/4072 , G11C5/06 , G11C8/10 , G11C8/14 , G11C16/08 , H01L27/112 , H01L27/11575 , H01L27/11582
摘要： Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
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公开(公告)号：US20200294598A1
公开(公告)日：2020-09-17
申请号：US16352824
申请日：2019-03-14
发明人： Kenneth Louie , Seok Tae Kim , Arka Ganguly , Qui Nguyen
摘要： Apparatuses, systems, methods, and computer program products are disclosed for reducing routing signals. An apparatus includes a first block decoder circuit that senses bad block data of a first latch circuit corresponding to a first memory block and couple the bad block data onto a bus. An apparatus includes a comparator circuit that compares the bad block data against a reference, sets a bad block flag, and routes the bad block flag on a routing line across an array of storage elements. An apparatus includes a second block decoder circuit that receives the bad block flag from the routing line, determines a condition of the first memory block based on the bad block flag, and determines a generation of a block selection signal for selecting a second memory block.
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公开(公告)号：US10115440B2
公开(公告)日：2018-10-30
申请号：US15625848
申请日：2017-06-16
发明人： Qui Nguyen , Alexander Chu , Kenneth Louie , Anirudh Amarnath , Jixin Yu , Yen-Lung Jason Li , Tai-Yuan Tseng , Jong Yuh
IPC分类号： G11C8/08 , G11C5/06 , H01L27/112 , G11C8/10 , G06F13/40
摘要： Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
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