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    Nonvolatile memory device with 3D memory cell array
    2.
    发明授权
    Nonvolatile memory device with 3D memory cell array 有权
    具有3D存储单元阵列的非易失性存储器件

    公开(公告)号：US08570808B2

    公开(公告)日：2013-10-29

    申请号：US13186987

    申请日：2011-07-20

    申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

    摘要翻译： 非易失性存储器件包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压信号的电压发生器电路，以及 行选择电路，其将所述第一电压信号同时施加到所选择的字线，并将所述第二电压信号施加到未选择的字线。 所选择的字线和未选字线具有不同的电阻，而第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

    NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY 有权
    具有3D存储单元阵列的非易失性存储器件

    公开(公告)号：US20120033501A1

    公开(公告)日：2012-02-09

    申请号：US13186987

    申请日：2011-07-20

    申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

    摘要： Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

    摘要翻译： 公开了一种非易失性存储器件，其包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压的电压发生器电路 信号和行选择电路，其将第一电压信号同时施加到所选字线，并将第二电压信号施加到未选字线。 所选择的字线和未选择的字线具有不同的电阻，但是第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

    Non-volatile memory device and method for programming the device, and memory system
    4.
    发明授权
    Non-volatile memory device and method for programming the device, and memory system 有权
    用于编程器件和存储器系统的非易失性存储器件和方法

    公开(公告)号：US08472247B2

    公开(公告)日：2013-06-25

    申请号：US13157344

    申请日：2011-06-10

    申请人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418

    摘要： A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.

    摘要翻译： 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。